Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Path: utzoo!mnetor!seismo!lll-lcc!pyramid!prls!mips!mash From: mash@mips.UUCP (John Mashey) Newsgroups: comp.arch Subject: Re: Japanese 32-bit CPUs Message-ID: <364@winchester.UUCP> Date: Tue, 5-May-87 02:19:09 EDT Article-I.D.: winchest.364 Posted: Tue May 5 02:19:09 1987 Date-Received: Wed, 6-May-87 01:31:59 EDT References: <3810030@nucsrl.UUCP> Reply-To: mash@winchester.UUCP (John Mashey) Organization: MIPS Computer Systems, Sunnyvale, CA Lines: 47 In article <3810030@nucsrl.UUCP> ram@nucsrl.UUCP (Renu Raman) writes: >... 3. Mitsubishi's 32 bit mP for their TRON project. > Some details > 1. No TLB > 2. RISCy (at least adhering to lean cycles, fixed format > simple instructions).... Re: TRON: See IEEE Micro, April 1987; whole issue on TRON project; esp. Ken Sakamura, "Architecture of the TRON VLSI CPU", 17-31. I wouldn't call the TRON architecture RISCy [note that this isn't saying good or bad, just that it tends to not be much like what most people think are RISC machines]: Fixed format instructions: not exactly: there are 16-bit instructions (short form), and then there are arbitrary-sized ones that are multiples of 16-bits. From my reading, they appear to allow arbitrary cascading of indirect addressing [like the Sperry 1100s, for example], which has interesting implications for pipelining. Thus, their addressing appears more complex than a 68020's. The architecture specifies a bunch of user-level instructions which compilers will find it difficult to generate: reverse-byte-order, search-for-zero-or-one, bitmap operations [not just bitfields, bit maps], string operations [including search for substring!], queue manipulation [insert, delete, search]. It also specs BCD operations. Note: I mean no criticism of the design, but if you call it RISC, then almost no machine is a CISC! In fact: ``What's a RISC?'' ANS: any machine announced since 1983. [This is clearly true, we've even been reading lately that the Motorola 68030 really has a lot of features expected to be found only on RISC machines. In particular, "One of the most basic concepts of RISC architectures is that of hardware support for instructions. The MC68020/MC68030, although not RISC processors, have an impressive amount of on-chip hardware for special instructions." T. L. Johnson, "The RISC/CISC Melting Pot", Byte, April 87. Huh? I always thought CPUs were there to provide hardware support for instructions....sigh.] -- -john mashey DISCLAIMER: UUCP: {decvax,ucbvax,ihnp4}!decwrl!mips!mash, DDD: 408-720-1700, x253 USPS: MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086