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Path: utzoo!mnetor!seismo!uwvax!cottage!lm
From: lm@cottage.WISC.EDU (Larry McVoy)
Newsgroups: comp.arch
Subject: Re: Japanese 32-bit CPUs ( NEC V70 )
Message-ID: <3530@spool.WISC.EDU>
Date: Tue, 5-May-87 16:32:19 EDT
Article-I.D.: spool.3530
Posted: Tue May  5 16:32:19 1987
Date-Received: Thu, 7-May-87 05:13:10 EDT
References: <3810030@nucsrl.UUCP> <491@necis.UUCP>
Sender: news@spool.WISC.EDU
Reply-To: lm@cottage.WISC.EDU (Larry McVoy)
Organization: U of Wisconsin CS Dept
Lines: 28

In article <491@necis.UUCP> geo@necis.UUCP (George Aguiar ext. 219) writes:
>The V-70 looks like a hell-of-a-chip.  Some other misc. hype:
>
>	- 32 General Registers ( all 32 bits of course )
>	- Symmetric Instruction Set
>	- 20 Addressing modes
>	- Variable Byte Length Format

Ummm, not to rain on your parade or anything - but I have real problems with 
the last two.  20 addressing modes?  That's a lot of logic.  And I'll bet
they support stuff like embedded displacements in the instruction stream (I'm
not talking about 4 bit constants, I'm talking about things like National 
and Motorola do with the top bits of their byte, word, and long word 
displacements).  That can cost you - you might not know off the top how long
the instruction is so your decoder might start decoding the previous 
instructions displacement(s).

Similar problem with the variable length format.  Unless they got smart and 
put the whole length as part of the first byte, you have to delay the logic 
that looks at the trailing part of the instruction.  This has messy 
implications when you consider the pipeline, does it not?

It looks like the 29K may have made some smart moves....

---
Larry McVoy 	        lm@cottage.wisc.edu  or  uwvax!mcvoy

"What a wonderful world it is that has girls in it!"  -L.L.