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From: pec@necntc.NEC.COM (Paul Cohen)
Newsgroups: comp.arch
Subject: Re: Japanese 32-bit CPUs ( NEC V70 )
Message-ID: <3972@necntc.NEC.COM>
Date: Tue, 5-May-87 17:14:35 EDT
Article-I.D.: necntc.3972
Posted: Tue May  5 17:14:35 1987
Date-Received: Thu, 7-May-87 05:30:34 EDT
References: <3810030@nucsrl.UUCP> <491@necis.UUCP>
Reply-To: pec@necntc.UUCP (Paul Cohen)
Organization: NEC Electronics Inc.  Natick, MA 01760
Lines: 49



>In article <3810030@nucsrl.UUCP> ram@nucsrl.UUCP (Renu Raman) writes:

>>	Japan's first microprocessor with 32-bit data and address buses
>>	The NEC V70 has a dynamic bus sizing that enables it to match
>>	input/output with 8,16, and 32 bit buses.  


>I have  some preliminary specs on the V70 and I quote:
>	"On-Chip Floating Point Support
>		- IEEE 32 and 64-Bit Data Types"
>	On-Chip MMU
>	On-Chip instruction and data cache

Sorry on this one point.  The preliminary specs you quote are in fact
very preliminary.  In order to get the product to market sooner, the V70
was designed without these caches.  Really, this is just a change of
names since the V70 + cache and other goodies will follow, but with a
different name, possibly V80.

>The V-70 looks like a hell-of-a-chip.  Some other misc. hype:

>	- 32 General Registers ( all 32 bits of course )
>	- Symmetric Instruction Set
>	- 20 Addressing modes
>	- Variable Byte Length Format
>	- Virtual Memory
>		4.3 GB Virtual Space / task
>		2 level paging
>		16 Entry Full Association 

>It's not iAPX386 compatible, this looks like a NICE architecture!!



Say that again: 

		*****************************************
		*****************************************
		***				      ***
		***   THE V70 IS NOT 386 COMPATIBLE   ***
		***				      ***
		***   THE V60 IS NOT 286 COMPATIBLE   ***
		***				      ***
		*****************************************
		*****************************************

this is a NICE architecture