Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Path: utzoo!utgpu!water!watnot!watmath!clyde!rutgers!lll-lcc!pyramid!prls!mips!mash From: mash@mips.UUCP Newsgroups: comp.arch,comp.sys.nsc.32k Subject: Re: the NS32532 Message-ID: <278@winchester.mips.UUCP> Date: Sat, 11-Apr-87 18:23:16 EST Article-I.D.: winchest.278 Posted: Sat Apr 11 18:23:16 1987 Date-Received: Sun, 12-Apr-87 17:39:15 EST References: <4190@nsc.nsc.com> Reply-To: mash@winchester.UUCP (John Mashey) Organization: MIPS Computer Systems, Sunnyvale, CA Lines: 69 Xref: utgpu comp.arch:838 comp.sys.nsc.32k:50 In article <4190@nsc.nsc.com> roger@nsc.nsc.com (Roger Thompson) writes: > First off let me introduce myself. I'm the technical marketing > manager for the Series 32000 product line..... > Yes, it is true that all we have today are simulated results. > But we have more than just a simulation model.... > For my friend Landon at Amdahl, I would like to say that the > simulated dhrystones results we published are real. Since > he asked several pointed questions, I'll provide results > du jour if you wish. > Let me give you some details ------ > 32332 @ 15 MHZ version 1.0 optimized ............ 3943.5 > 32332 @ 15 MHZ version 1.1 optimized ............ 3183.0 > 32332 @ 15 MHZ version 1.1 no global opt......... 2724.0 > > 32532 @ 30 MHZ version 1.0 optimized ............ 19800 > 32532 @ 30 MHZ version 1.1 optimized ............ 16600 > 32532 @ 30 MHZ version 1.1 no global opt ........ 14100 Since these were volunteered to the net, let me suggest a few things that will help credibility and let people assess the reality of these numbers. Simulations can be OK: people who scoff at them automatically are being a little harsh, although past histories of many vendors leads to skepticism. Here are the suggestions: 1) Since 1.0 Dhrystones have been obsolete for over a year, and clearly labeled as such by every issue of Rick R's postings, is there some nonobvious reason why 1.0 numbers are included? 2) This posting fixes a problem with an earlier one in this sequence <417@nsc.nsc.com>, which claimed around 18K simulated Dhrystones: "Just for interest, simulated Dhrystone performance of around 18,000 with on chip physical-address instruction and data caches, and on board demand- paged MMU..." Thank you for giving the correct labeling: from these numbers, it appears that the earlier posting claimed Dhrystone figures that were 1.0 ones, WITHOUT LABELING THEM AS SUCH. If this is not true, please correct this impression. If it is true, I'd suggest that people in this newsgroup especially have learned to be pretty skeptical for exactly this kind of thing. 3) When publishing performance figures of microprocessors, if there is to be ANY semblance of credibility, you MUST specify the memory system hooked to the micro as modeled in the simulations, and give other environmental issues. Here is a starting list: cache size(s) data cache nature: write-thru [maybe with write buffers], or write-back cache line sizes number of cycles penalty for refilling the caches, refill nature main memory DRAM speed used in the model to achieve the above. environment: standalone, or in simulated virtual memory environment, including MMU overhead, if any, and something for OS overhead [like clock ticks that execute code that trashes the caches now and then]. [A bunch of this is very relevant to what real performance one will see on real benchmarks: Dhrystone is amenable to small caches.] 4) Once again, just to introduce some reality, what this means is that the 20MHz parts will, in 4Q87 (more-or-less, for the usual reasons), run at about 2/3 the numbers show above. Hence, we'd hope to see posted to the list some real machine numbers, that following the usual Dhrystone rules, rate a 20MHz, unoptimized 1.1 Dhrystone at around 9400 and an optimized one at around 11000. Hence, given the usual intervals, maybe in mid-88 we'll see real machine numbers in the 14000 - 16000 range, which should be respectable, if not spectacular for that time. -- -john mashey DISCLAIMER: UUCP: {decvax,ucbvax,ihnp4}!decwrl!mips!mash, DDD: 408-720-1700, x253 USPS: MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086