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From: top@tub.UUCP
Newsgroups: comp.arch
Subject: 68020-Cache-Question - (nf)
Message-ID: <48000004@tub.UUCP>
Date: Sat, 11-Apr-87 09:41:00 EST
Article-I.D.: tub.48000004
Posted: Sat Apr 11 09:41:00 1987
Date-Received: Wed, 15-Apr-87 00:42:43 EST
Lines: 23
Nf-ID: #N:tub:48000004:000:604
Nf-From: tub!top    Apr 11 15:41:00 1987

I have a question for all 68020-insiders:

How many external bus accesses does a 68020 make running such loop:

    LOOP: bra LOOP

Our MC68020 did following:

One (1) cache cycle, One (1) external bus cycle.
Do *YOU* know why ?

I forgot: "program" address was 0x300000, we found it using
an Oscilloscope (no software-timing-guesses).

If you have any ideas just let me know. If you respond in E-mail,
you may answer in German (if you wish ;-)

Thanks!

Thomas Patzelt, Gesellschaft fuer Mathematik und Datenverarbeitung (GMD)
		Technical University of Berlin (W-Germany).

     ...seismo!unido!tub!top