Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Path: utzoo!utgpu!water!watmath!clyde!rutgers!im4u!oakhill!davet From: davet@oakhill.UUCP Newsgroups: comp.arch,comp.sys.nsc.32k Subject: Re: NS32532 Patents Message-ID: <863@oakhill.UUCP> Date: Wed, 15-Apr-87 03:39:55 EST Article-I.D.: oakhill.863 Posted: Wed Apr 15 03:39:55 1987 Date-Received: Fri, 17-Apr-87 00:02:41 EST References: <4206@nsc.nsc.com> Reply-To: davet@oakhill.UUCP (Dave Trissel) Organization: Motorola Inc. Austin, Tx Lines: 69 Xref: utgpu comp.arch:878 comp.sys.nsc.32k:68 In article <4206@nsc.nsc.com> roger@nsc.nsc.com (Roger Thompson) writes: > > The specifics of the NS32532, however are unprecedented in 32-bit >microprocessor architectures. In fact National has applied for >eigth separate patents on the NS32532: Only eight patents? I'm just a software guy and I was associated with four patent applications for the MC68020. What follows is not a critique of the NS32532 at all, just a comment on your highly touted list of architectural breakthroughs. Remember, I'm only a software guy so Motorola may have already done some of the other things in your list I don't address. But if you take into consideration all of the other microprocessor firms representing themselves in this newsgroup, I would be rather suprized if your list doesn't turn to zip. >1.) The method of detecting and handling memory-mapped I/O > by a pipelined microprocessor. ----- Think about > that for a while. The 32532 has a 1024 byte 2 way set > associative data cache. Without the special method > of handling I/O, writing I/O drivers is somewhat problematic. Motorola offers this via several means. First, a non-cachable bit in our MMU descriptor can be used to indicate I/O space. Second, a class of instructions which lock the bus automatically avoid using on-chip cache. Third, external hardware can signal any bus cycle to be non-cached thus forcing the next reference to again come out onto the external bus. >3.) Monitoring control flow in a microprocessor ----- in other > words, branch prediction. The MC68010 (out about 5 years now?) supported this for it's DBcc set of branch instructions (loop mode.) Yes it was more primitive, but the idea is the same. >5.) Method of simultanous references to the cache and Bus Interface unit. The MC68020 does this. Instruction references go to both the on chip cache and to the bus controller. The bus controller aborts it's cycle if the cache comes up with the data. >6.) Method for completing instructions without waiting for writes. ---- > Yes thats right. Reads have priority over writes. Writes are > buffered in a 2 entry FIFO. There is one exception to this > rule ----- memory mapped I/O as in patent # 1 above. The MC68020 has a one buffer write mechanism. Intel claims that both their 286 and 386 chips support a one buffer write queue also. >7.) Method of optimizing instruction fetches. Most latter day microprocessors could make this claim. Do you have unique logic on the part to accomplish this? >8.) MMU that is accessible by the instruction unit, address unit > and the execution unit. Again, unique logic on the part is necessary for a patent here. >I'm open to discussion on any of these unique attributes. > >------- Roger First you need to establish just what is unique or not. -- Dave Trissel Motorola Semiconductor Inc., Austin, Texas {ihnp4,seismo}!ut-sally!im4u!oakhill!davet