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From: bcase@amdcad.UUCP
Newsgroups: comp.arch
Subject: Update to word addressing
Message-ID: <16163@amdcad.AMD.COM>
Date: Wed, 15-Apr-87 12:40:10 EST
Article-I.D.: amdcad.16163
Posted: Wed Apr 15 12:40:10 1987
Date-Received: Fri, 17-Apr-87 03:04:08 EST
Organization: Advanced Micro Devices, Inc., Sunnyvale, Ca.
Lines: 22

Well, I just got a mail message from one of our circuit designers.  While
I don't consider his comments "officially binding" or anything (by that I
mean he might later want to change his mind or modify what he said), I
presume they are reasonably well considered.  He said that by and large
John Mashey's comments were correct:  It isn't very costly in terms of
time to have the byte alignment network on the chip.  One implementation
technique is to have the byte alignment network control decoded as the
address leaves the chip so that when the data comes back there is only
a propagation delay, not a decode plus prop delay.

I can think of some issues which would still need to be resolved, but
they are probably resolvable.  The effect on setup and hold times is my
biggest worry (strange words from someone considered to be a software
type!).  The point, though, is that I may have spoken a little strongly
and a little quickly.

I must say that I *still* feel comforable with our design.  I must also
say that these net discussions have been quite enlightening and have
humbled me just a bit (any more humble and I'll only be able to speak
in a mumble).

    bcase