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From: gerryg@laidbak.UUCP (Gerry Gleason)
Newsgroups: comp.arch
Subject: Re: An idea I'm kicking around
Message-ID: <1057@laidbak.UUCP>
Date: Mon, 20-Apr-87 00:10:44 EST
Article-I.D.: laidbak.1057
Posted: Mon Apr 20 00:10:44 1987
Date-Received: Tue, 21-Apr-87 01:21:07 EST
References: <12884@watnot.UUCP> <136@tmsoft.UUCP>
Reply-To: gerryg@laidbak.UUCP (Gerry Gleason)
Distribution: comp
Organization: LAI Chicago
Lines: 12

In article <136@tmsoft.UUCP> mason@tmsoft.UUCP (Dave Mason) writes:
>I'm not sure if this is currently in use by anyone, but I've also thought of
>it in a RISCy stack machine (no, I don't think a conflict in terms) that I've
>been doing thought experiments with.

There is one I know of, CRISP (C Reduced Instruction Set Processor) at
AT&T.  I did some work on the kernel for a experimental prototype of
this machine.  It's basically a risc processor with a top of stack cache.  
It seemed like a good architecture, but I don't know what they are doing
with it.

gerry gleason