Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Path: utzoo!mnetor!seismo!rutgers!ames!pioneer!lamaster From: lamaster@pioneer.arpa (Hugh LaMaster) Newsgroups: comp.arch Subject: Re: 64 Vs 32 Message-ID: <1316@ames.UUCP> Date: Mon, 20-Apr-87 16:26:31 EST Article-I.D.: ames.1316 Posted: Mon Apr 20 16:26:31 1987 Date-Received: Tue, 21-Apr-87 03:08:58 EST References: <3810013@nucsrl.UUCP> <28200016@ccvaxa> Sender: usenet@ames.UUCP Reply-To: lamaster@ames-pioneer.arpa (Hugh LaMaster) Organization: NASA Ames Research Center, Moffett Field, Calif. Lines: 54 Keywords: address size, physical memory limits, RAM disks Two items: The April 1987 Anderson Report describes IBM's new announcement of production 4 Mbit chips. It quotes a report by the California Technology Stock Letter which claims that by 1994 small and medium magnetic disk drives will be obsolete. I know that we have heard it before, but in any case, the progress in high density memory is not slowing down yet (I'm sure everyone has heard that 16Mbit prototypes now exist also). The technology necessary for much larger memory systems is now in the pipeline. My guess is: you can expect 64MB workstations within 4 years and 256MB systems within 8 years. The second item: National Advanced Systems has now announced 2Gigabyte physical memory systems (the limit of 32 bit 370/XA). This amount of memory is consistent with the systems now being shipped with performance on the order of 100MIPS (whatever a MIP is). Amdahl has 1GB systems and IBM 512 MB systems today. If a 1 MIP system a few years ago needed 16MBytes of virtual and 4 MBytes of physical memory (my own figures), a 100MIP system needs about 2GB of virtual and 512 MBytes of physical memory. Therefore, a 4 processor system with 4 100MIP CPU's (this is my estimate for the coming generation of high end systems) will need 8 GB of virtual and 2GB physical memory; this is more than the limit of 32 bit addressing processors. I think we have settled the question earlier of whether everyday applications exist for lots of memory and address space (high quality graphics alone is sufficient in many cases, even without another application to display). Now, we see that the technology is here to exceed 32 bit addressing. Recent experience has shown that architecturally, "small" systems like workstations have come to resemble their larger cousins more and more (real operating systems, virtual memory, multiprogramming, etc. etc.) Therefore, I expect to see the first 64 bit linear addressed microprocessor about 4 years from now. I hope I'm not disappointed :-) Naturally, the machine will have 64 bit registers, with both 32 bit and 64 bit integer and floating point formats supported with hardware on chip. The first versions will probably have a 64 bit bus/data path, but within a few years expect to see 256 bit data paths. Within 8 years from now, we should expect to see a 1 million gate load/store version with a vector instruction set and segmented arithmetic and logic functional units. On chip instruction cache, of course. In other words, a current supercomputer on a chip. This estimate is based on current or near term projected technology. How about it- think it can be done? Hugh LaMaster, m/s 233-9, UUCP {seismo,topaz,lll-crg,ucbvax}! NASA Ames Research Center ames!pioneer!lamaster Moffett Field, CA 94035 ARPA lamaster@ames-pioneer.arpa Phone: (415)694-6117 ARPA lamaster@pioneer.arc.nasa.gov "In order to promise genuine progress, the acronym RISC should stand for REGULAR (not reduced) instruction set computer." - Wirth ("Any opinions expressed herein are solely the responsibility of the author and do not represent the opinions of NASA or the U.S. Government")