Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Path: utzoo!utgpu!water!watnot!watmath!clyde!rutgers!ames!ucbcad!ucbvax!csri.toronto.EDU!moraes From: moraes@csri.toronto.EDU.UUCP Newsgroups: comp.lsi Subject: Re: SPICE time-step too small Message-ID: <8704150041.AA22773@csri.toronto.edu> Date: Tue, 14-Apr-87 19:41:55 EST Article-I.D.: csri.8704150041.AA22773 Posted: Tue Apr 14 19:41:55 1987 Date-Received: Thu, 16-Apr-87 01:13:42 EST Sender: daemon@ucbvax.BERKELEY.EDU Distribution: world Organization: The ARPA Internet Lines: 55 Russ Foster (foster@huey.udel.edu) raises what must be an old and well- known SPICE problem. To get SPICE to converge on some circuits seems to require the services of your friendly neighbourhood warlock 8-) Some tricks which seem to work (sometimes!) are: 1. Try SPICE2F.1! Analog circits like op-amps often refuse to work with the 2G or 3 family. But they do work on 2F.1. Question: What is the difference in the F and G versions? Are the results of 2F inaccurate? They LOOK ok. 2. For DC convergence, raise the temperature, or re-arrange the nodes numbers so that SPICE sets its internal matrices up differently. This is suggested in "The Design and Analysis of VLSI Circuits" by Glasser and Dobberpuhl. I've found it sometimes works, presumably because the raised temperature lowers the gain of the circuit, which is something else suggested in the book. There is a neat Appendix on "Spice Techniques" in it. 3. Try changing TRTOL to a larger number, which sometimes works, or VNTOL. Oddly enough, changing ABSTOL from 1 picoamp to 1 nanoamp seems to cause SPICE to die faster! 4. If you're into simulation and FORTRAN, try hacking around in dctran.f which is where the Internal Timestep Too Small error originates. But be prepared for a big task! Question: At a really small timestep, like 1e-15 secs, a CMOS circuit shold be doing absolutely nothing (well, except for a few electrons here or there!) Even for a stiff problem, SPICE shold not complain too much at this time-step. After all, the trapezoidal method is A-stable and guarantees not to blow up even for relatively large time-steps. So why can't SPICE just go ahead with a warning message? 5. Either strip off the really small capacitors (anything less than 100ff is usually redundant) which circuit extractors tend to tag on to internal nodes, by setting a threhold or something. Those "stiffen" the problem, and probably cause SPICE to lower the time-step. Alternatively, increase them with some sort of fudge value. If you're into dynamic circuits, the latter course may produce spurious charge sharing, if the internal caps start getting near the order of the output node caps. And the former course may cause you to miss some charge sharing, if for example you have an output node of 0.05pF and you knock off a 0.01pF cap on a connected internal node. Proceed with caution. I'd be interested to know how the problem is really solved, and if anyone knows precisely why this happens. As far as I know, one plays around with any or all of the above till SPICE accepts the circuit. Does anyone have a source code fix? Any SPICE gurus out there know an answer? How about a collection of SPICE techniques? Anyway, that's my two cents worth. Hope it helps. Mark Moraes. (moraes@csri.toronto.edu, moraes@utcsri.uucp)