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From: greenberg@decsim.DEC.COM.UUCP
Newsgroups: comp.lsi
Subject: Re: SPICE time-step too small
Message-ID: <8704151403.AA16347@decwrl.dec.com>
Date: Wed, 15-Apr-87 12:50:00 EST
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Posted: Wed Apr 15 12:50:00 1987
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> What is the difference in the F and G versions?

For analog MOS circuits, the difference is a change in the implementation of
the Ward capacitance model.  The matrix techniques in the G versions should be
more robust than in the F versions.

>3. Try changing TRTOL to a larger number

This would cause SPICE to take larger time steps.  I think the only reason why
this would work is that it is a random shift that gets SPICE away from the
particular model glitch that is causing problems.

>Question: At a really small timestep, like 1e-15 secs, a CMOS circuit
>shold be doing absolutely nothing (well, except for a few electrons
>here or there!) Even for a stiff problem, SPICE shold not complain too
>much at this time-step. After all, the trapezoidal method is A-stable
>and guarantees not to blow up even for relatively large time-steps. So
>why can't SPICE just go ahead with a warning message?

A glitch in the current versus voltage equation of a model causes tremendous
problems which only get worse as the time step gets smaller.  A glitch is a
constant delta V no matter how small the delta t, so the current gets huge.
This behavior is contrary to the expected error behavior of the numerical
methods where the error of Newton-Raphson and the error of the integration
formulae get smaller with smaller time-step.

Even if you stay away from the Ward capacitance model and use the Meyer model
you are going to run into problems.  There is a potential glitch problem around
VDS=0.

>How about a collection of SPICE techniques? 

Fix the model bugs is my recommendation.  This may not be too practical a
recommendation because these types of bugs are very hard to find.  Barring
that, all the recommendations that have been made so far are probably
reasonable ways to mask the problem.

/Steve