Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Path: utzoo!mnetor!seismo!columbia!rutgers!ucla-cs!fan From: fan@CS.UCLA.EDU Newsgroups: comp.os.minix Subject: Re: EMS spec Message-ID: <5700@shemp.UCLA.EDU> Date: Mon, 27-Apr-87 10:18:38 EDT Article-I.D.: shemp.5700 Posted: Mon Apr 27 10:18:38 1987 Date-Received: Tue, 28-Apr-87 01:42:59 EDT References: <497@gouldsd.UUCP> <5664@shemp.UCLA.EDU> <19@netxcom.UUCP> Sender: root@CS.UCLA.EDU Reply-To: fan@CS.UCLA.EDU (Roy Fan) Organization: UCLA Computer Science Department Lines: 57 Keywords: so how *does* it work ? >>(1) the EMS ramdisk can have a maximum of 1MB since the pointer >>they use is only 16 bits (the segment). This doesn't seem right >>though, there might be something I miss. > >Actually, an EMS board can have 2MB of memory, and there can be four of >them. Some EMS boards can have 4MB of memory, but look just like two >2MB boards to the driver. Sorry I didn't make myself clear. When I said about the 'pointer', I meant the pointer used in Minix. Doesn't the pointer has only 16 bits (I forgot the type name, physical_click or something like that). If only 16 bits are available, specifying a segment, doesn't that only give us 20 bits address, which is 1 Megabytes. Perhaps that we could have 2 EMS ramdisk? >>(2) you will need an EMS driver that will map the logical memory >>into the 64K physical memory. For a very simple ramdisk driver, I was >>thinking of mapping the first bank to the beginning of the logical >>memory, and the rest 3 banks after that. That way, you will have a >>minimum of 48K to transfer. And if the process requests more than >>48K, you could break them into parts. > >If you use all four page registers sequentially, then you could use >DMA to move up to an entire segment from EMS to memory, and vice versa. I don't think that we could use DMA to do memory to memory transfer in the IBM PC. >Is this so? I though that the page registers were accessed through the >I/O addresses: 2[0-F]8 and 2[0-F]9, depending upon switch settings, with >two extra significant address bits (bit 14 and bit 15), providing access >to the four page registers at I/O addresses: 02[x]8, 42[x]8, 82[x]8 and >C2[x]8. As I understood it, the xxx8 addressed page registers contain the >EMS page number being mapped, and the xxx9 addressed page registers >contain the "page frame", ie: the segment address to which that EMS page >is mapped, so that: > >Finally, since the entire F000 segment is reserved for ROM, isn't it >unlikely that any registers would be placed there? Can anyone out >there clear this up? The JRAM-3 board from Tall Tree is a successor of the JRAM-2 board. JRAM-2 board was introduced before the Lotus/Intel/Microsoft EMS, it used bank switching. The JRAM-3 is compatible with EMS specification and it can be used as 64K bank switching instead of just 4 16K. They have the so-called control register that will map any 64K from the board to any 64K in IBM's 1MB memory. The control register is located at any unused memory location, such as F800, E800, etc. The reason that they may use F800:0000 as the control register is that ROM is readable, but the control register is only writable. So if you do a READ on F800:0000 you got the ROM codes, but if you do a write on F800:0000, the ROM won't get changed because it is ROM, but it will affect the control register. Roy Fan University of California fan@cs.ucla.edu Los Angeles