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From: darrell@sdcsvax.UUCP
Newsgroups: comp.os.research,mod.os
Subject: Re: Life with TLB and no PT
Message-ID: <3038@sdcsvax.UCSD.EDU>
Date: Fri, 24-Apr-87 11:40:53 EST
Article-I.D.: sdcsvax.3038
Posted: Fri Apr 24 11:40:53 1987
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Organization: Advanced Micro Devices, Inc., Sunnyvale, Ca.
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In article <3031@sdcsvax.UCSD.EDU> lamaster@pioneer.arpa (Hugh LaMaster) writes:
+-----
| Another question:  The minimum requirements for support of Capabilities
| seems to be:
| 
| 1) Virtualizable instruction set architecture
| 2) Hardware control to permit read-only access.  
| 
| Do any of the new machines in question qualify on both counts?
| (e.g. am29000, MIPS R-2000, Celerity . . .)
+-----
The Am29000 processor is fully "virtualizable"; all privileged
instructions are trapped with a protection violation in such a way that
the privileged instruction can be examined and executed for the "virtual
machine" by the "real machine", and the virtual machine's instruction
stream can be restarted correctly.

The protection bits provided in the TLB entries are:

	SR	-- supervisor read permission
	SW	-- supervisor write permission
	SE	-- supervisor execute permission

	UR	-- user read permission
	UW	-- user write permission
	UE	-- user execute permission

So the answer is "yes" on both counts.


	-- Tim Olson
	Advanced Micro Devices
	Processor Strategic Development
	(tim@amdcad.AMD.COM)