Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP
Path: utzoo!utgpu!water!watmath!clyde!rutgers!husc6!uwvax!oddjob!hao!ames!ucbcad!ucbvax!sdcsvax!darrell
From: darrell@sdcsvax.UUCP
Newsgroups: comp.os.research
Subject: Re: Life with TLB and no PT
Message-ID: <3085@sdcsvax.UCSD.EDU>
Date: Tue, 5-May-87 06:05:42 EDT
Article-I.D.: sdcsvax.3085
Posted: Tue May  5 06:05:42 1987
Date-Received: Thu, 7-May-87 02:11:28 EDT
Lines: 30
Approved: mod-os@sdcsvax.uucp

> ... The memory management hardware in the Sun-2
> architecture has 8 contexts, but no TLB...

[We should note that BAD things happen on a SUN if there are > 8  contexts -DL]

Actually, an alternate view of the Sun MMUs is that they are very large
software-managed TLBs done in a slightly unusual way.  The first stage
of address translation (segment map) is the equivalent of the associative
lookup of a more orthodox TLB.  The second stage (page map) is identical
to normal TLB address translation.  The correspondence is actually quite
close, to the point where one can envision semi-portable memory-management
code that treats the Sun MMU as if it were a big TLB.  The large size of
the maps is a way around the relatively high overhead of doing TLB update
in software with processors not designed for it.  The 8-contexts business
minimizes TLB flushes, which are expensive with a TLB that big.

On the more general topic of TLBs with no PTs, note also Cheriton's recent
MMUless design, in which a software-updated virtual-address cache eliminates
mapping hardware altogether.

				Henry Spencer @ U of Toronto Zoology
				{allegra,ihnp4,decvax,pyramid}!utzoo!henry



-- 
Darrell Long
Department of Computer Science & Engineering, UC San Diego, La Jolla CA 92093
ARPA: Darrell@Beowulf.UCSD.EDU  UUCP: darrell@sdcsvax.uucp
Operating Systems submissions to: mod-os@sdcsvax.uucp