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From: darrell@sdcsvax.UUCP
Newsgroups: comp.os.research,mod.os
Subject: Re: Life with TLB and no PT
Message-ID: <3031@sdcsvax.UCSD.EDU>
Date: Thu, 23-Apr-87 13:55:00 EST
Article-I.D.: sdcsvax.3031
Posted: Thu Apr 23 13:55:00 1987
Date-Received: Sat, 25-Apr-87 07:32:24 EST
Sender: darrell@sdcsvax.UCSD.EDU
Organization: NASA Ames Research Center, Moffett Field, Calif.
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Xref: utgpu comp.os.research:7 mod.os:136

The discussion about TLB's with no hardware PT brings up the following
remark/suggestion:

It is possible (and has been done) for the TLB to allow multiple
simultaneous page sizes.  This has a lot of attraction for
engineering/scientific users (us folks who use floating point :-)
because typical code segments are much smaller than data segments.
This allows code to live on small pages, data to live on large pages,
and the page tables to be kept small even when the machine memory gets
very, very big.  Try it; your users will like it.  If you don't do
something like this, you will need a very large (expensive in all
relevant senses) TLB to handle simple cases like accessing big arrays
along the second or third dimension.  A big TLB  may also increase
context switch time excessively.

Another question:  The minimum requirements for support of Capabilities
seems to be:

1) Virtualizable instruction set architecture
2) Hardware control to permit read-only access.  

Do any of the new machines in question qualify on both counts?
(e.g. am29000, MIPS R-2000, Celerity . . .)


  Hugh LaMaster, m/s 233-9,  UUCP {seismo,topaz,lll-crg,ucbvax}!
  NASA Ames Research Center                ames!pioneer!lamaster
  Moffett Field, CA 94035    ARPA lamaster@ames-pioneer.arpa
  Phone:  (415)694-6117      ARPA lamaster@pioneer.arc.nasa.gov

"In order to promise genuine progress, the acronym RISC should stand 
for REGULAR (not reduced) instruction set computer." - Wirth

("Any opinions expressed herein are solely the responsibility of the
author and do not represent the opinions of NASA or the U.S. Government")