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From: rajiv@im4u.UUCP
Newsgroups: comp.arch,comp.sys.nsc.32k,comp.sys.intel,comp.sys.m68k
Subject: Re: Question:  on-chip or off-chip MMU?
Message-ID: <1774@im4u.UUCP>
Date: Thu, 23-Apr-87 22:45:36 EST
Article-I.D.: im4u.1774
Posted: Thu Apr 23 22:45:36 1987
Date-Received: Sat, 25-Apr-87 08:45:03 EST
References: <5635@shemp.UCLA.EDU>
Reply-To: rajiv@im4u.UUCP (Rajiv N. Patel)
Organization: U. Texas CS Dept., Austin, Texas
Lines: 53
Xref: utgpu comp.arch:1025 comp.sys.nsc.32k:110 comp.sys.intel:172 comp.sys.m68k:374

Summary:More suggestions and views on this issue.

In article <5635@shemp.UCLA.EDU> fan@CS.UCLA.EDU (Roy Fan) writes:
>--------------
>	I am doing a project on MMU's, and from reading various uP
>data books, I have several questions:
>
>	It seems that the trend is putting the MMU on-chip.  68020 has
>no on-chip MMU, but 68030 has a subset of MMU.  iAPX 386 has MMU on
>chip, and so is the National Semiconductor 32532 (I haven't read the
>data books yet, so I might be mistaken).  Fairchild Clipper has an
>off-chip MMU.
>
>	Question 1 :  are there any other factors that might affect the
>design of the MMU being on-chip or off-chip?
>
>	Question 2 :  if there is enough space on the chip, would
>everybody put the MMU on-chip?
>
>	Question 3 :  if there is only enough room for either a cache
>or a MMU, which one will prevail?
>

I seem to agree about the trend for putting the MMU on-chip and I feel that
chip area would be a governing factor to the decision for placing the MMU on
the chip. 

There may be an issue raised regarding the rigidity of translation mechanisms
faced by on-chip MMU's if variable paging schemes(elaborate control) are not
available in this hardware.I am not very familiar with this issue but feel that
it might play a role in the decision for on-chip or off-chip MMU.
Ofcourse, still it is very attractive (speed gains) to place the MMU on-chip.
This would be the case for full system design products, like the  IBM PC RT for
instance, where the translation and page sizes are decided by the same company
that designs the MMU.

As regarding the choice between an on-chip cache and an on-chip MMU is concerned
I would choose to place both these on the chip but as the area is limited I 
would make a compromise by placing ONLY the TLB of the MMU on-chip (translation
and page tables of-chip) and a smaller cache in the remaining real estate.
The reason for this is that the TLB if of reasonable size would give around 60%
hits and a small cache would also give atleast 60-70% hits, this way we get the
best of both the cache and MMU operations.
The above choice is very dependant on the speed up one can obtain between 
on-chip and of-chip accesses. But I feel a compromizing decision would work
better than going one way.

Well that's some of my views ,I do not have some magic numbers to support them
but would be happy to receive comments and criticism regarding them.


Rajiv.

ARPA: rajiv@im4u.utexas.edu
UUCP: {ihnp4,seismo,allegra,ucbvax}!ut-sally!im4u!rajiv