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From: ihm@nrcvax.UUCP (Ian H. Merritt)
Newsgroups: comp.sys.m68k,comp.sys.intel
Subject: Re: Re: Re: Recent Motorola ad seen in Byte
Message-ID: <884@nrcvax.UUCP>
Date: Tue, 28-Apr-87 14:12:24 EDT
Article-I.D.: nrcvax.884
Posted: Tue Apr 28 14:12:24 1987
Date-Received: Sat, 2-May-87 02:44:31 EDT
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Reply-To: ihm@minnie.UUCP (Ian Merritt)
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Xref: mnetor comp.sys.m68k:434 comp.sys.intel:215

>>
>[ comparison of 11's and 80x8y's ]
>> 
>> Integer Divides and multiplies (on models that had them) had to use even/odd
>> register pairs.  MMU registers were memory mapped (which I would call "wierd".
>> Early PDP-11s could not shift more than one bit per instruction.  The 80x86
>> instruction set has more serious register limitiations than the variable
>> shift count (which is rarely used).  Even worse are its dedicated use of SI,
>> DI, and AX for the string instructions.
>
>This is not peculiar to Intel as NSC 32xxx and Dec VAX machines do it 
>(probably a lot of others) as well. Each dedicates particular registers
>for specific (count, dst., src.) functions in string instructions. It
>is the only way to have single instruction string operations that are
	^^^^
>interruptible and resumable (which you obviously want) other than
>perhaps putting the internal (non user visible) microcode registers
>on the stack *every* time an interrupt happens (*yuck*).

The ONLY way?  Really?  First off, it is not clearly desirable to have
single instruction dedicated string operations, particularly if the
processor can execute a short loop just as fast (or faster), the
latter providing far greater flexibility.  If for some reason, you
must have a single instruction, though, it is perfectly reasonable to
have the instruction SPECIFY the source, destination, and count
registers (or whatever operands the instruction requires), thereby
allowing ANY GENERAL PURPOSE REGISTER (not something found on Intel
processors) to be used for any operand.

On another note, wrt the PDP-11 multiply/divide stuff, I was
particularly disturbed when they decided to have a mixed-endian model.
Basically, the PDP-11 is a little-endian processor where the low-order
byte of a word is in the lower numbered address, and bits are numbered
as powers of two.  When they had to store 32 bit numbers, for
multiplies and divides, they decided to deviate from this basically
consistent philosophy, storing the high order word in the lower
numbered address; the low word in the higher, but within these words,
the bytes are stored the other way.  Terriffic.  The reasons for this
have oft been discussed, and I do not wish to spark another such
conversation, but it sure was confusing.


Cheerz--
							<>IHM<>