Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Path: utzoo!mnetor!seismo!rutgers!mit-eddie!uw-beaver!ubc-vision!fornax!chapman From: chapman@fornax.uucp (John Chapman) Newsgroups: comp.sys.m68k,comp.sys.intel Subject: Re: Re: Re: Recent Motorola ad seen in Byte Message-ID: <274@fornax.uucp> Date: Sat, 2-May-87 03:34:28 EDT Article-I.D.: fornax.274 Posted: Sat May 2 03:34:28 1987 Date-Received: Sun, 3-May-87 05:44:43 EDT References: <930@intsc.UUCP> <1517@ncr-sd.SanDiego.NCR.COM> Distribution: comp Organization: School of Computing Science, SFU, Burnaby, B.C. Canada Lines: 93 Xref: mnetor comp.sys.m68k:438 comp.sys.intel:218 . . > >> shift count (which is rarely used). Even worse are its dedicated use of SI, > >> DI, and AX for the string instructions. > > > >This is not peculiar to Intel as NSC 32xxx and Dec VAX machines do it > >(probably a lot of others) as well. Each dedicates particular registers > >for specific (count, dst., src.) functions in string instructions. It > >is the only way to have single instruction string operations that are > ^^^^ > >interruptible and resumable (which you obviously want) other than > >perhaps putting the internal (non user visible) microcode registers > >on the stack *every* time an interrupt happens (*yuck*). > > The ONLY way? Really? First off, it is not clearly desirable to have Yes the only way to have : single instruction, interruptible, and resumable string instructions without putting extra microcode internal registers on the stack at interrupts. Yes it is obviously desirable for string instructions to be resumable. If you have to stack extra internal state then: 1. either you only stack the stuff when a string instruction is interrupted so your stack state on interrupt is dependant on the instruction being interrupted - this is undesirable, or 2. you always stack that information whether it's needed or not introducing a general overhead to interrupts to accomodate the occasional string instruction. > single instruction dedicated string operations, particularly if the > processor can execute a short loop just as fast (or faster), the > latter providing far greater flexibility. If for some reason, you 1. how would you code a string instruction like FFS (find first set bit) to fit in something like the 68010's single instruction looping feature/cache? 2. with good code cacheing and instruction pipelining you *might* get the same performance with a multi-instruction equivalent to the simpler string instructions; cases where single instructions execute slower than multi-instruction equivalents are more likely to be indicative of other problems, e.g. poor micro-coding of the single instruction. > must have a single instruction, though, it is perfectly reasonable to > have the instruction SPECIFY the source, destination, and count > registers (or whatever operands the instruction requires), thereby > allowing ANY GENERAL PURPOSE REGISTER (not something found on Intel > processors) to be used for any operand. But it *isn't* perfectly reasonable. The guys who design these chips aren't stupid you know - they do this stuff for a reason. A good pipelined cpu will have simultaneous opcode and operand decode. The architecture is optimized around a central issue like this; a two address machine has it's silicon designed to handle one or two operand decodes efficiently. So along comes a string instruction with 3 or 4 operands - now what do you do? If you want full operand generality then the chip has to have real estate dedicated to handle these (few) exceptional instructions with extra operands. Why is it necessary to have full generality for these instruction operands? You know in advance what you will be using a calculation result for so do it in the register it needs to be in. You have all the other registers to do what you want with so why is it a problem that (for example) the vax uses low numbered registers for string operands? What exactly does it prevent you from doing? Also part of the reason I posted my original response was that you were flaming at Intel fro dedicating certain registers for certain functions. I have two problems with this: 1. as originally pointed out this is hardly unique to Intel so if you are going to flame about it you better flame everybody else who does it too - unless of course you are biased. 2. most people present this as "well you have to use SI as string source register" (implying that that is the only use for SI or DI, or BX or BP), rather than "well you can do general arithmetic etc. on SI and if you want to do a string instruction you use SI as the source operand". . . . > > Cheerz-- > <>IHM<> *** REPLACE THIS LINE WITH YOUR MESSAGE *** -- {watmath,seismo,uw-beaver}!ubc-vision!fornax!sfulccr!chapman or ...!ubc-vision!sfucmpt!chapman