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From: randy@pecnos.UUCP
Newsgroups: comp.sys.m68k
Subject: CAS/CAS2 mapping to VME RMW
Message-ID: <344@pecnos.UUCP>
Date: Thu, 23-Apr-87 15:25:31 EST
Article-I.D.: pecnos.344
Posted: Thu Apr 23 15:25:31 1987
Date-Received: Sat, 25-Apr-87 09:03:02 EST
Organization: Concurrent Computer Corp. Tinton Falls, N.J.
Lines: 48


I have a question of the VME/68020 gurus out there.

This question relates to how CAS and CAS2 are being implemented using
the VME bus since they don't directly map to the defined bus control
structure for indivisible cycles.

As with the 68000 and 68010, the TAS of the 68020 maps into the RMW type
of cycle of the VME bus. Likewise the single operand CAS also maps into
the RMW.

The problem comes when the CAS or CAS2 uses multiple operands and does
not map into the RMW cycle.  This is because multiple different addresses 
may be used and so AS- on the VME bus must be toggled, thus defeating the 
mechanism which keeps the RMW cycles indivisible.

One way to solve this is to detect these types of CAS and CAS2 cycles
and have the boards bus requester hold BUSY- on the VME bus throughout
the processor cycle (i.e. while RMC- of the 68020 is asserted)  and
release when the cycle is done. 
This works fine for single ported memories, but...

The problem with this is for dual ported memories.  These may be either
processor boards with dual-ported local memory or a memory board
dual-ported to the VME bus and another bus (e.g. VMX).

In order to make the access to the memory indivisible, the dual-port arbiter
must lock to the selected port not only on VME AS- (like for a RMW cycle)
but also lock on VME BUSY-.  Again this is something that can be done.
The problem comes about when a release-on-request board is used (ROR).
Since this type of requester holds BUSY- asserted until another bus master
request the bus, a dual-port arbiter would "lock-up" on the VME bus
access even though the CAS cycle is over.  This lock-up will lock out any 
accesses from the other port (i.e. the processor or other bus). Bad news!

I have also seen another solution to mapping the CAS/CAS2 cycles to the VME
bus which uses the reserved pin on connector P2 to drive RMC- from the 68020
onto the bus. This is a great solution except it is not part of the VME spec
and standard VME boards know nothing about this extra signal.

The bottom line question is: How are VME 68020 boards implementing CAS/CAS2
to dual-ported memory without locking things up for an undetermined amount
of time?  (Besides not using ROR type bus masters)
I have studied several boards and have not seen a satisfactory solution.

Thanks for any insight you may have.

Randy Banton