Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Path: utzoo!utgpu!water!watmath!clyde!rutgers!lll-lcc!styx!ptsfa!ihnp4!occrsh!occrsh.ATT.COM!gorgo.UUCP!authorplaceholder From: authorplaceholder@gorgo.UUCP.UUCP Newsgroups: comp.sys.m68k Subject: Re: Question: on-chip or off-chip MMU? Message-ID: <58500002@gorgo.UUCP> Date: Sun, 26-Apr-87 18:40:00 EDT Article-I.D.: gorgo.58500002 Posted: Sun Apr 26 18:40:00 1987 Date-Received: Wed, 29-Apr-87 06:05:43 EDT References: <5635@shemp.UCLA.EDU> Lines: 25 Nf-ID: #R:shemp.UCLA.EDU:-563500:gorgo.UUCP:58500002:000:981 Nf-From: gorgo.UUCP!bsteve Apr 26 17:40:00 1987 This is (of course) a very fuzzy question. I would tend to go (for now) with an off-chip mmu for several reasons: 1) On-board MMUs require micro-bus cycles just like separate MMUs, and depending upon the uP architecture may take the same number of cycles. 2) We can't add virtual cache with an on-board MMU. The advantage of virtual over physical cache is that it operates in parallel with the MMU cycles and returns in nearly half the time on a hit, whereas the physical cache always requires a complete MMU cycle. 3) Some applications (small signal processing, etc.) don't really require the MMU, so why should one drive up the cost of the uP by adding one on-board? 4) Some architectures support stackable multiple MMUs that operate parallel. One obviously cannot do this if the MMU is on-board. I am sure that there are numerous other reasons why off-chip MMUs are more desirable. Steve Blasingame (Oklahoma City) ihnp4!gorgo!bsteve