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From: roger@nsc.UUCP
Newsgroups: comp.arch,comp.sys.nsc.32k
Subject: NS32532 Patents
Message-ID: <4206@nsc.nsc.com>
Date: Tue, 14-Apr-87 01:27:08 EST
Article-I.D.: nsc.4206
Posted: Tue Apr 14 01:27:08 1987
Date-Received: Wed, 15-Apr-87 04:51:00 EST
Organization: National Semiconductor, Sunnyvale
Lines: 50
Xref: utgpu comp.arch:865 comp.sys.nsc.32k:61

To stimulate some more valued discussions, let me lift some
of what is discussed in the 32532 overview brochure;

"  At least a dozen manufacturers have brought 32-bit solutions to the
marketplace.  While each design is similar in the broad view, the specifics
of each implementation can vary greatly.  And it is those specifics
that determine which is best for your needs.

   The specifics of the NS32532, however are unprecedented in 32-bit
microprocessor architectures.  In fact National has applied for 
eigth separate patents on the NS32532:

1.)  The method of detecting and handling memory-mapped I/O
     by a pipelined microprocessor.  ----- Think about
     that for a while.  The 32532 has a 1024 byte 2 way set
     associative data cache.  Without the special method
     of handling I/O, writing I/O drivers is somewhat problematic.

2.)  Maintaining coherence between a microprocessors integrated cache
     and the external memory.  ------ Since both the Instruction
     and Data caches are physical caches, we were able to devise
     a means to provide "hardware" cache coherence hooks.  Coherency
     can be maintaind without cubersome software overhead and at
     cost in performance.

3.)  Monitoring control flow in a microprocessor ----- in other 
     words, branch prediction.

4.)  The concept of a fully integrated cache, Memory Management Unit,
     and Instruction pipeline.

5.)  Method of simultanous references to the cache and Bus Interface unit.

6.)  Method for completing instructions without waiting for writes. ----
     Yes thats right.  Reads have priority over writes.  Writes are
     buffered in a 2 entry FIFO.  There is one exception to this
     rule ----- memory mapped I/O as in patent # 1 above.

7.)  Method of optimizing instruction fetches.

8.)  MMU that is accessible by the instruction unit, address unit
     and the execution unit.

   These unique and innovative architectural refinements give the
NS32532 key performance advantages in a variety of 32-bit applications."


I'm open to discussion on any of these unique attributes.

------- Roger