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From: hansen@mips.UUCP
Newsgroups: comp.arch,comp.sys.nsc.32k
Subject: Re: NS32532 Patents
Message-ID: <299@dumbo.mips.UUCP>
Date: Tue, 14-Apr-87 19:26:05 EST
Article-I.D.: dumbo.299
Posted: Tue Apr 14 19:26:05 1987
Date-Received: Thu, 16-Apr-87 01:02:10 EST
References: <4206@nsc.nsc.com> <18308@ucbvax.BERKELEY.EDU>
Distribution: na
Lines: 19
Keywords: branch prediction, cache coherence, microprocessor, cache
Xref: utgpu comp.arch:872 comp.sys.nsc.32k:66
Summary: what is claimed is....

In article <18308@ucbvax.BERKELEY.EDU>, shebanow@ji.Berkeley.EDU (Mike Shebanow) writes:
> In article <4206@nsc.nsc.com> roger@nsc.nsc.com (Roger Thompson) writes:
> >   The specifics of the NS32532, however are unprecedented in 32-bit
> >microprocessor architectures.  In fact National has applied for 
> >eigth separate patents on the NS32532:
> Sorry for creating a flame letter, but maybe I am confused about
> what is being patented here. Are you claiming that the concepts above
> are patentable, or that the methods used to reduce the concepts to practice
> are patentable?

Seems to me that all Roger said was that National has applied for these
patents. For all we know, the applications might be rejected because they
are considered either not "novel" or because they are judged to be "obvious
to one skilled in the state of the art."
-- 
Craig Hansen
Manager, Architecture Development
MIPS Computer Systems, Inc.
...decwrl!mips!hansen