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From: shebanow@ji.Berkeley.EDU (Mike Shebanow)
Newsgroups: comp.arch,comp.sys.nsc.32k
Subject: Re: NS32532 Patents
Message-ID: <18308@ucbvax.BERKELEY.EDU>
Date: Tue, 14-Apr-87 10:45:19 EST
Article-I.D.: ucbvax.18308
Posted: Tue Apr 14 10:45:19 1987
Date-Received: Sun, 19-Apr-87 00:08:39 EST
References: <4206@nsc.nsc.com>
Sender: usenet@ucbvax.BERKELEY.EDU
Reply-To: shebanow@ji.Berkeley.EDU.UUCP (Mike Shebanow)
Distribution: na
Organization: University of California, Berkeley
Lines: 51
Keywords: branch prediction, cache coherence, microprocessor, cache
Summary: This is patentable???
Xref: mnetor comp.arch:961 comp.sys.nsc.32k:78

In article <4206@nsc.nsc.com> roger@nsc.nsc.com (Roger Thompson) writes:
>   The specifics of the NS32532, however are unprecedented in 32-bit
>microprocessor architectures.  In fact National has applied for 
>eigth separate patents on the NS32532:
>
>1.)  The method of detecting and handling memory-mapped I/O
>     by a pipelined microprocessor.  ----- Think about
>     that for a while.  The 32532 has a 1024 byte 2 way set
>     associative data cache.  Without the special method
>     of handling I/O, writing I/O drivers is somewhat problematic.

What happens in a VAX??? It has the same problem. How about the
680X0?? Same thing again. The simple solution is to have a bit in the
page table entry saying that this is I/O. That way, the data is uncached.
Is there something wrong with this solution?

>2.)  Maintaining coherence between a microprocessors integrated cache
>     and the external memory.  ------ Since both the Instruction
>     and Data caches are physical caches, we were able to devise
>     a means to provide "hardware" cache coherence hooks.  Coherency
>     can be maintaind without cubersome software overhead and at
>     cost in performance.

This is new for a microprocessor, but not in general. Is what you are
doing a different method for cache coherency (Archibald and Baer in
the Nov. 86 ACM Transactions on Computer Systems has a good survey)?

>3.)  Monitoring control flow in a microprocessor ----- in other 
>     words, branch prediction.

This again is new for a micro, but not in general. What type of branch 
prediction are you doing (Lee and Smith IEEE Computer Jan. 84, MacFarling
and Hennesy 13th ISCA June 86, JE. Smith 8th SCA 81, IBM <too many to list>)?

>6.)  Method for completing instructions without waiting for writes. ----
>     Yes thats right.  Reads have priority over writes.  Writes are
>     buffered in a 2 entry FIFO.  There is one exception to this
>     rule ----- memory mapped I/O as in patent # 1 above.

Again, I don't understand what is new and unique. This is a well known
technique. Alan Smith in his '83 (82???) ACM paper on "CPU Cache Memories"
describes such a write buffer being used to improve write-through cache
performance.

Sorry for creating a flame letter, but maybe I am confused about
what is being patented here. Are you claiming that the concepts above
are patentable, or that the methods used to reduce the concepts to practice
are patentable?

Mike Shebanow
(shebanow@ji.berkeley.edu)