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From: mash@mips.UUCP (John Mashey)
Newsgroups: comp.sys.nsc.32k
Subject: Re: NS32310 Vs NS32381
Message-ID: <323@winchester.UUCP>
Date: Mon, 20-Apr-87 18:25:35 EST
Article-I.D.: winchest.323
Posted: Mon Apr 20 18:25:35 1987
Date-Received: Wed, 22-Apr-87 00:38:52 EST
References: <145@unsvax.UUCP> <4221@nsc.nsc.com>
Reply-To: mash@winchester.UUCP (John Mashey)
Organization: MIPS Computer Systems, Sunnyvale, CA
Lines: 12

In article <4221@nsc.nsc.com> roger@nsc.nsc.com (Roger Thompson) writes:
>	2.)  The 32381 is an active project due out of fab in
>	     the mid summer time frame. It is based on the 32081
>	     but is done in CMOS and will operate at up to 30 MHZ.......
>	     up adds and multiplies.  Double precision floating
>	     multiplies can be done in 1 usec at 30 MHZ.
Just out of curiosity, are there timings/cycle counts available for
adds, divides?  [This looks like 33 cycles for a DP multiply?]
-- 
-john mashey	DISCLAIMER: <generic disclaimer, I speak for me only, etc>
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