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From: grenley@nsc.nsc.com (George Grenley)
Newsgroups: comp.arch,comp.sys.nsc.32k
Subject: Re: Performance of the 532
Message-ID: <4300@nsc.nsc.com>
Date: Fri, 8-May-87 15:12:06 EDT
Article-I.D.: nsc.4300
Posted: Fri May  8 15:12:06 1987
Date-Received: Sat, 9-May-87 20:45:55 EDT
References: <324@dumbo.UUCP> <809@killer.UUCP> <2417@homxa.UUCP> <4294@nsc.nsc.com> <374@winchester.UUCP> <3552@spool.WISC.EDU>
Reply-To: grenley@nsc.UUCP (George Grenley)
Organization: National Semiconductor, Sunnyvale
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Xref: mnetor comp.arch:1222 comp.sys.nsc.32k:142

In the interests of brevity,
I have deleted a lot from Larry's posting, much of it comments by John 
Mashey.  If you haven't been following the discussion, do go back and
catch up.

In article <3552@spool.WISC.EDU> lm@cottage.WISC.EDU (Larry McVoy) writes:
>    Icache is 512 bytes, 32 lines, direct mapped.
>    Dcache is 1024 bytes, 64 lines, 2 way set associative, write through.
>    TLB is 64 entries, fully associative.

Correct.  However, there is also an external cache, described by me in a
previous posting.

>Also, I'm a little surprised at the figures.  I just spent a bit of time
>going over the data book and I would have expected better numbers.  
>Closer to 8-10 MIPS...  Bummer....

If you can get 10 mips we may have a job for you...
Seriously, our simulation was based on a real-world Unix environment, with
context switches, etc. - Difficult to model by hand.  I am sure that
well-written code without a lot of system overhead and cold-cache problems
will hit 10 mips.