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From: kadkade@decsim.dec.com
Newsgroups: comp.arch
Subject: To RISC or to CISC .....
Message-ID: <9801@decwrl.DEC.COM>
Date: Sun, 10-May-87 22:23:00 EDT
Article-I.D.: decwrl.9801
Posted: Sun May 10 22:23:00 1987
Date-Received: Mon, 11-May-87 04:46:20 EDT
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Organization: Digital Equipment Corporation
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In article <1516@drivax.UUCP> tyler@drivax.UUCP (William Tyler) writes:
>>Code size is important because the size of the code determines how much
>>memory traffic is generated by instruction fetches (exclusive of improvements
>>due to caching).  All other things being equal, fewer bytes of code lead
 
Comment by lm@cottage.wisc.edu  or  uwvax!mcvoy>
>Excuse me, but I think you need to look at cache performance a little bit
>more.  Last *I* heard, given a reasonable icache, you could count on about a
>90-99% hit ratio.  Think about that for a momement...  If you never executed
>the same instruction twice then the hit ratio would be 0%, right?  So that
>suggests if one is getting a 90% hit ratio that instruction is being used a
>lot, right?  So if you throw in a cache that gives you 90% hits then you've
>just decreased memory traffic (instruction only, but a similar argument
>applies for data) to 10% of what it was with no cache....
 
I suppose if you had long loops, or similar code then given a more tightly
packed instruction set (CISC) would help, so that the code in the cache would
be replaced less frequently. Or in the case of RISC you would need a larger
cache, which would make such systems costlier. Though, by how much I don't
know. In any case I think the preceding argument is still valid if cache is
expensive.

The argument goes on about pipelining helping RISC machines and indeed being
a part of RISC. Didn't pipelining exist long before the acronym RISC was
coined? Pipelining is used in CISC machines, too. Are there are reasons to 
believe that pipelining provides is a greater reason for efficiency in RISC
machines than CISC machines.

Shouldn't the arguments on the instruction set and micro-architecture get
down to trying to figure out what instructions on CISC machines cause
problems (I-stalls, too much silicon, etc.) and how they should be replaced
rather than a RISC vs. CISC slugfest? Can there be such a compromise? Seems
to me that the main benefit of the RISC architectures to the CISC architects
has been to have to justify every instruction they throw into the box.

Thanx,
Sudhir.

The above are my personal opinions - at this moment anyway - and should 
not be construed as DEC's positions on this or any other subjects.