Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP
Path: utzoo!mnetor!seismo!gatech!amdcad!tim
From: tim@amdcad.AMD.COM (Tim Olson)
Newsgroups: comp.arch
Subject: Re: Japanese 32-bit CPUs ( NEC V70
Message-ID: <16649@amdcad.AMD.COM>
Date: Tue, 12-May-87 15:05:48 EDT
Article-I.D.: amdcad.16649
Posted: Tue May 12 15:05:48 1987
Date-Received: Fri, 15-May-87 01:21:22 EDT
References: <372@winchester.UUCP> <28200037@ccvaxa>
Reply-To: tim@amdcad.UUCP (Tim Olson)
Organization: Advanced Micro Devices, Inc., Sunnyvale, Ca.
Lines: 21

In article <28200037@ccvaxa> preece@ccvaxa.UUCP writes:
+-----
| The point isn't that RISCs make certain optimizations easier or harder,
| but that they make certain optimizations NECESSARY. ...
+-----
No, the point is that RISCs make certain optimizations *POSSIBLE* -- by
using only simple, single-cycle instructions, optimization opportunities
are uncovered which may not be available with complex, multi-cycle
instructions -- especially in loops.

+-----
|                                                 ...  Compilers smart
| enough to use some of the special features of CISCs haven't been
| sufficiently necessary -- they work "well enough" using simple
| instruction sequences.  ...
+-----
And those simple instruction sequences allow higher levels of one of the
most beneficial optimizations -- code motion out of loops.

	-- Tim Olson
	Advanced Micro Devices