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From: jeff@felix.UUCP (Jeff Wallace)
Newsgroups: comp.arch,comp.sys.m68k
Subject: Re: 68020 speeds and wait states
Message-ID: <2728@felix.UUCP>
Date: Tue, 12-May-87 11:36:55 EDT
Article-I.D.: felix.2728
Posted: Tue May 12 11:36:55 1987
Date-Received: Fri, 15-May-87 02:40:36 EDT
References: <5635@shemp.UCLA.EDU> <1774@im4u.UUCP>, <814@killer.UUCP> <2106@hoptoad.uucp>
Organization: FileNet Corp., Costa Mesa, CA
Lines: 17
Summary: 68030 cache fill
Xref: mnetor comp.arch:1261 comp.sys.m68k:476

> ...I suspect
> he'd have more luck with the 68030 since it does burst fetches into
> cache, which can be fed quickly with static column RAMs without building
> a whole board full of cache like the 3/260.

	I believe the 68030 cache fill requires the use of ripple-mode DRAMs
unless one wishes to generate the lower address signals external during
this process.  While on the subject, what are ripple-mode DRAMs popular
for?  Although the ripple cycle time is typically faster than that for
static column or page mode devices the fact that the ripple sequence uses
rowA8 and colA8 seems to prevent sequencial access, doesn't it?  Doesn't
it seem more logical to use colA1 and colA0?

-- 
					  Jeff Wallace
				{decvax,ucbvax}!trwrb!felix!jeff
				  FileNet Corp. Costa Mesa, CA