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From: phil@amdcad.UUCP
Newsgroups: comp.arch,comp.sys.m68k
Subject: Re: 68020 speeds and wait states
Message-ID: <16650@amdcad.AMD.COM>
Date: Tue, 12-May-87 22:30:53 EDT
Article-I.D.: amdcad.16650
Posted: Tue May 12 22:30:53 1987
Date-Received: Fri, 15-May-87 06:40:58 EDT
References: <5635@shemp.UCLA.EDU> <1774@im4u.UUCP> <814@killer.UUCP> <2106@hoptoad.uucp> <2728@felix.UUCP>
Reply-To: phil@amdcad.UUCP (Phil Ngai)
Organization: Advanced Micro Devices, Inc., Sunnyvale, Ca.
Lines: 44
Xref: utgpu comp.arch:1178 comp.sys.m68k:444

In article <2728@felix.UUCP> jeff@felix.UUCP (Jeff Wallace) writes:
>	I believe the 68030 cache fill requires the use of ripple-mode DRAMs
>unless one wishes to generate the lower address signals external during
>this process.

You must be talking about nibble mode. There is one company (Vitelic)
offering a ripplemode but it is not what you think. Their ripplemode
means the access time is mostly determined from when a stable column
address is ready rather than from when CAS is activated. Column
address access time is 55 nS while CAS access time is only 25 nS. The
column address is latched when CAS is activated; this makes address
pipelining easier and page mode faster. Page cycle times of 75 nS
(plus data setup time on the device using the data) are no sweat.
Contrast this to ordinary page mode, where first you have to provide
CAS precharge, set up the column address, and then access time is
determined from CAS activation, for a minimum cycle time of 120 nS. 

Ripplemode is almost as nice as static column access DRAMs.

> While on the subject, what are ripple-mode DRAMs popular
>for?  Although the ripple cycle time is typically faster than that for
>static column or page mode devices the fact that the ripple sequence uses
>rowA8 and colA8 seems to prevent sequencial access, doesn't it?  Doesn't
>it seem more logical to use colA1 and colA0?

You can use the pins as you see fit. The pin police will not arrest
you for reassigning the values. 

To be specific, you are assuming that your system's A0, A1, A2, etc
are mapped: A0 -> colA0, A1 -> colA1, A8 -> colA8, A9 -> rowA0, etc.

Just move the wires around to give: A0 -> colA8, A1 -> rowA8, and
connect the rest of the pins in any convenient way. 

If you want to understand why the nibble mode works the way it does,
read the chip's operation description. 

TI has a data sheet on an extended nibble mode DRAM, TMX4C1029, which
gives 1024 bits in nibble mode. This looks like it could be VERY
useful, particularly for AMD's 29000 which has a burst mode protocol
on its instruction and data bus. 

-- 
Phil Ngai, {ucbvax,decwrl,allegra}!amdcad!phil or amdcad!phil@decwrl.dec.com