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From: hansen@mips.UUCP (Craig Hansen)
Newsgroups: comp.arch
Subject: Re: [really CISC] (no, really, the AMD 29k claims)
Message-ID: <388@dumbo.UUCP>
Date: Wed, 13-May-87 23:11:30 EDT
Article-I.D.: dumbo.388
Posted: Wed May 13 23:11:30 1987
Date-Received: Sat, 16-May-87 07:51:09 EDT
References: <3810030@nucsrl.UUCP> <491@necis.UUCP> <3530@spool.WISC.EDU> <16658@amdcad.AMD.COM>
Distribution: world
Lines: 35
Summary: Enough hogwash already

In article <16658@amdcad.AMD.COM>, phil@amdcad.AMD.COM (Phil Ngai) writes:
> Let's not forget about a branch target cache. With memories capable of
> supplying high bandwidth (nibble mode, page mode, video memories, etc)
> all you really need is to handle the start up time. By caching only
> about four instructions at the branch target, you can run loops at
> full speed no matter how long they are. By caching several branch
> targets you can handle nested loops, etc. 

Don't forget that you must interleave load and store references into that
memory system too.  A "real man's" memory system with ECC, of a serious
size, and bandwidth for I/O transactions doesn't respond to a memory request
in 80 nanoseconds.  (This assumes two cycles in on/off chip delays and
branch target selection).  This means that you'd better cache more than four
instructions in your branch target cache, and the average basic block size
is in the range of six to eight instructions (This is for MIPS instructions,
AMD instructions would be more because of their weaker load/store/branch
instructions).  The branches that terminate these basic blocks are taken
more than 50% of the time, so I don't see how a branch target cache performs
comparably to an instruction cache, in a real system environment.

I guess the AMD folks are excited about their new child, but when reality
sets in, and you try to build a real UNIX-based computer system out of this
fine controller part, you'll be sorely disappointed if you expected 17 MIPS
at 25 MHz with a nibble-mode DRAM as your primary memory system.  Based on
their benchmarks (puzzle, dhrystone, and a tiny piece of linpack; sorry, but
that's all they've got to compare with...) with an external cache, external
cache control hardware, and a fast main memory system, a 29000 at 25 MHz that
you can build next year doesn't perform any faster than a MIPS R2000 system
at 16.7 MHz that you can build now.

-- 
Craig Hansen
Manager, Architecture Development
MIPS Computer Systems, Inc.
...decwrl!mips!hansen