Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP
Path: utzoo!mnetor!seismo!ll-xn!ames!pioneer!lamaster
From: lamaster@pioneer.arpa (Hugh LaMaster)
Newsgroups: comp.arch
Subject: Re: I-cache prefetch
Message-ID: <1551@ames.UUCP>
Date: Thu, 14-May-87 21:24:34 EDT
Article-I.D.: ames.1551
Posted: Thu May 14 21:24:34 1987
Date-Received: Sat, 16-May-87 12:18:08 EDT
References: <765@apple.UUCP>
Sender: usenet@ames.UUCP
Reply-To: lamaster@ames-pioneer.arpa (Hugh LaMaster)
Organization: NASA Ames Research Center, Moffett Field, Calif.
Lines: 35

>>(Has anyone ever made a machine the pre-fetches I-cache lines from memory?)

The CDC Cyber 7600 and 176, possibly other later Cybers (865/875), 
(7600 designed by Cray, others derived from that design),
all Crays,
the Cyber 205 (entirely different architecture machine from CDC)
and derivative machines (ETA-10),

all had I - cache prefetch.  

An earlier machine, the CDC 6600, had instruction STACK (not exactly 
a cache) prefetch.  

In most of the above instances, two "words" (each word with 2-16
instructions depending on the machine) were prefetched.  The technique
has been used on other high performance machines as well.  It may have
been used on the IBM 360/91 and 360/195.  Anyway, the technique is at
least 23 years old if you count the 6600.  It works, too :-)  

Instruction prefetch is one of the many performance benefits derived
when you separate the instruction cache and the data cache.




  Hugh LaMaster, m/s 233-9,  UUCP {seismo,topaz,lll-crg,ucbvax}!
  NASA Ames Research Center                ames!pioneer!lamaster
  Moffett Field, CA 94035    ARPA lamaster@ames-pioneer.arpa
  Phone:  (415)694-6117      ARPA lamaster@pioneer.arc.nasa.gov

"In order to promise genuine progress, the acronym RISC should stand 
for REGULAR (not reduced) instruction set computer." - Wirth

("Any opinions expressed herein are solely the responsibility of the
author and do not represent the opinions of NASA or the U.S. Government")