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From: brucek@hpsrla.HP.COM (Bruce Kleinman)
Newsgroups: comp.arch
Subject: Re: Re: Japanese 32-bit CPUs ( NEC V70 ) [really CISC]
Message-ID: <3460001@hpsrla.HP.COM>
Date: Thu, 14-May-87 23:19:55 EDT
Article-I.D.: hpsrla.3460001
Posted: Thu May 14 23:19:55 1987
Date-Received: Sun, 17-May-87 11:51:56 EDT
References: <3561@spool.WISC.EDU>
Organization: Network Measurements Div - Santa Rosa, CA
Lines: 60


+-----
| Any operation can be done faster if implemented at a 'lower' level in 
| the machine.
+-----

Completely true.  The problem is there is only so much 'lower' level.
Chip real estate isn't unlimited, at least it wasn't last time I checked.

CISC chips frequently offer hundreds of instructions with a dozen or more
address modes.  This usually necessitates the use of one, sometimes two,
levels of microcode.  The richness/complexity of the instruction set
requires a mass of pipeline interlock logic.  CISC CPUs tend to be, uh,
rather complex.  And, therefore, the CPU usually dominates the chip.

RISC chips generally offer a hundred or fewer instructions with a few
address modes.  This usually allows the instruction set to be hardwired.
The orthogonal nature of the instruction set requires very little
pipeline interlock logic.  RISC CPUs tend to be rather simple. And,
therefore, the CPU is usually a small portion of the chip.

The CISC advocate interprets the quote at the top of this note and says,
   " Putting 'register indirect with base + offset' addressing in the
     instruction set is a win, because my chip will be able to do it
     with a single instruction -- which will make my chip really fast. "
This approach buys you some very useful operations at the expense of
real estate.  Your instruction set soon becomes less orthogonal, more
exceptions are introduced, and you have to handle them in the pipeline
logic.  Pretty soon you are out of real estate, because you have a big
chunk or two of microcode, a large area for decode, and a gate array
worth of logic to glue your pipeline together ....

The RISC advocate interprets the quote and says,
   " Leaving 'register indirect with base + offset' addressing out of
     the instruction set is a win, because I will be able to hardwire
     the CPU -- which will make my chip really fast. "
This approach buys you a very orthogonal instruction set, while using
up relatively little real estate.  Your CPU is hardwired, most instructions
execute in a single cycle, and your pipeline can be balanced more easily.
And you've got a bunch of real estate left over ....

Who wins?

My (completely unbiased) answer:
The RISC chip wins because the extra real estate can be used for a massive
register file, or an on chip floating point unit, or a *real* cache
(i.e. one greater than 256 bytes), etc, etc.  

Yes, any operation can be done faster if implemented at a 'lower' level in 
the machine.  And a RISC chip leaves you a lot of 'lower' level to work
with after the CPU is complete.  And I'll take a 192 registers or a 4K 
cache over 'register indirect with base + offset' any day.

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
                              Bruce Kleinman
              Hewlett Packard -- Network Measurements Division
                          Santa Rosa, California

                         ....hplabs!hpsrla!brucek
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~