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From: pec@necntc.NEC.COM (Paul Cohen)
Newsgroups: comp.arch
Subject: Re: To RISC or to CISC .....(was V60/V70...)
Message-ID: <4709@necntc.NEC.COM>
Date: Mon, 18-May-87 16:49:21 EDT
Article-I.D.: necntc.4709
Posted: Mon May 18 16:49:21 1987
Date-Received: Tue, 19-May-87 04:48:00 EDT
References: <9801@decwrl.DEC.COM>
Reply-To: pec@necntc.UUCP (Paul Cohen)
Organization: NEC Electronics Inc.  Natick, MA 01760
Lines: 27



In Article <1204lm@cottage.WISC.EDU> writes:

>Excuse me, but I think you need to look at cache performance a little bit
>more.  Last *I* heard, given a reasonable icache, you could count on about a
>90-99% hit ratio.  

>So if you throw in a cache that gives you 90% hits then you've
>just decreased memory traffic 


In the context of the current discussion concerning microprocessor 
architecture, a memory access should be defined as any access to the 
memory SYSTEM and that includes any access to an off-chip cache.  I may
be showing my ignorance, but I am not aware of any on-chip icaches that 
get anything approaching 90% hit ratios.  In addition, in order to be 
fair, you should not count as a hit any cache access that would have 
missed had there been no pre-fetching into the cache (since the pre-
fetching generates memory traffic).  Such pre-fetching is often a 
significant contributor to these kinds of hit ratios.


> But look at what CISC is costing DEC

Again I may be showing my ignorance, but I thought DEC's balance sheet
was in pretty good shape these days.