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From: baum@apple.UUCP (Allen J. Baum)
Newsgroups: comp.arch
Subject: Re: Japanese 32-bit CPUs ( NEC V70 ) [really CISC]
Message-ID: <782@apple.UUCP>
Date: Mon, 18-May-87 14:05:02 EDT
Article-I.D.: apple.782
Posted: Mon May 18 14:05:02 1987
Date-Received: Tue, 19-May-87 05:41:33 EDT
References: <609@csun.UUCP> <1920@dg_rtp.UUCP>
Reply-To: baum@apple.UUCP (Allen Baum)
Organization: Apple Computer, Inc.
Lines: 19

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[]

>In the first place, the main thing about ALL of the RISC's that are true
>RISC's, is that EVERY instruction takes one cycle.  No exceptions.
>Another thing that the RISC philosophy has come to mean
>is regular (ie, no special purpose accumulator's, any register can be the
>target or source(s) of any instruction).

I hate to disappoint you, but I can't think of any RISC machines that
meet these (rather Ad Hoc) criteria. Most of the RISC processors out
there have multi-cycle instructions, including the original RISC I,
which had a two cycle load, and most of them have a register which is
a hard-wired zero. The HP Spectrum has at least two instructions with
hardwired register destinations. The definition of 'RISC' is in the mind
of the beholder. There is no 'agreed' definition of what a  RISC processor
is except that maybe you know one when you see one.....

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