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From: jps@apollo.uucp (Jeffrey P. Snover)
Newsgroups: comp.arch
Subject: Re: Japanese 32-bit CPUs ( NEC V70 ) [really CISC]
Message-ID: <34f454ee.8be4@apollo.uucp>
Date: Tue, 19-May-87 09:21:00 EDT
Article-I.D.: apollo.34f454ee.8be4
Posted: Tue May 19 09:21:00 1987
Date-Received: Wed, 20-May-87 04:47:34 EDT
References: <609@csun.UUCP> <1920@dg_rtp.UUCP> <782@apple.UUCP>
Organization: Apollo Computer, Chelmsford, Mass.
Lines: 17


>The definition of 'RISC' is in the mind
>of the beholder. There is no 'agreed' definition of what a  RISC processor
>is except that maybe you know one when you see one.....
 
It seems to me that the progression of things goes something like this:
    - Come up with a new angle on things
    - Pick a flashy aspect and name the set of ideas after it
        ( RISC is easier to say than OIPC [One Instruction Per Cycle] 
          and flashier than NM [No Microcode])
    - Evolve the concept, expanding on the good ideas and passing on the
      not so good ideas.
    - Spend years complaining when the evolved idea doesn't comform 
      to the flashy name.
        o the idea was bast***ized
        o thats not a *REAL* xxxx
        o the damn trilateral commission is at it again!