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From: bcase@apple.UUCP
Newsgroups: comp.arch
Subject: Re: To RISC or to CISC .....(was V60/V70...)
Message-ID: <798@apple.UUCP>
Date: Wed, 20-May-87 13:08:43 EDT
Article-I.D.: apple.798
Posted: Wed May 20 13:08:43 1987
Date-Received: Fri, 22-May-87 01:08:20 EDT
References: <9801@decwrl.DEC.COM> <4709@necntc.NEC.COM> <3604@spool.WISC.EDU>
Reply-To: bcase@apple.UUCP (Brian Case)
Organization: Apple Computer Inc., Cupertino, USA
Lines: 15

In Article <1204lm@cottage.WISC.EDU> writes:
>So if you throw in a cache that gives you 90% hits then you've
>just decreased memory traffic 

I should have responded when this was originally posted.  A cache often
does, but does not necessarily, lower memory traffic.  In particular,
when the block size (the minimum transfer quantum, I mean) is large,
as it is for relatively large caches with few tags, even low miss rates
can require lots of bandwidth. A totally bogus, but illustrative,
example is a 4K cache with one tag: even if the miss rate is only 1%,
you can see that the reload bus bandwidth requirement is almost 100%.
Techniques like one valid bit per word (or few words) can mitigate
the effect.

    bcase