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From: bcase@apple.UUCP (Brian Case)
Newsgroups: comp.arch
Subject: Re: Branch Target Cache vs. Instruction Cache
Message-ID: <790@apple.UUCP>
Date: Tue, 19-May-87 15:15:26 EDT
Article-I.D.: apple.790
Posted: Tue May 19 15:15:26 1987
Date-Received: Sat, 23-May-87 03:29:04 EDT
References: <3810030@nucsrl.UUCP> <491@necis.UUCP> <3530@spool.WISC.EDU> <781@apple.UUCP>
Organization: Apple Computer, Inc., Cupertino, USA
Lines: 54
Summary: I screwed up

In article <781@apple.UUCP>, bcase@apple.UUCP (Brian Case) writes:

A bunch of garbage.  I don't know on what drug I was, but I be trying
that one again.  Let me make summarize some corrections pointed out by
Phil Ngai.

> How about 80ns 256K DRAMs, interleaved two-way.  With these RAMs (available
> at Fry's for $7 each, so proabably for $4 from a real suppler), the Am29000
> need have only *two* instructions in each branch target entry.

Well, I got the density and the price right, but that is about it.  There is
*no* way an 80 ns DRAM can give a 2 cycle first access.  The Am29000, like
any processor has clock-to-address-valid and set-up times.  Sheesh, sorry.
These DRAMs interleaved are still interesting, but because of DRAM cycle-
time constraints, more than two-way is probably necessary.

> We're not even talking about video DRAMs, which are probably cheaper than
> these high-speed guys.  But, video DRAMs are available at least
> in 120 ns versions, three 25 MHz Am29000 cycles, so it should still be
> possible, even considering that extra control logic may add a cycle to
> the first access.  I know that such RAMs are more expensive than
> pedestrian 256K DRAMs (by about a factor of 2), and this is a real
> consideration for some people, but a full main memory system can be built
> for real computers with these parts (look inside a Macintosh Plus or
> Mac II (UNIX, but not fantastic performance) for a lesson in minmalist
> deisgn).

It was pointed out that (at least some) VDRAMs have some bizzareness that
lengthens the apparent first access time.  Also, I seem to have implied
that the Mac uses VDRAMs for its main memory.  This is clearly not the
case!  I simply meant to say that the Mac is an example of minimalist
design (mostly for cheap, easy manufacturability).

> >We have publicly stated that we will improve the performance
> >of our products at a rate of doubling performance every eighteen months,
> >and our current product plans are running faster than that rate.
> >If I could ask, what happens to the Am29k bus at 40 to 55 MHz?
> 
> Well, if it were left alone, then its cycle time would scale and a device
> would have only 25 to 18 ns to respond.  25 is sorta reasonable, but
> 18 sounds pretty silly.

Sigh, again, at any clock speed, the time given to a memory to respond is
mitigated by clock-to-address-valid and set-up times.  At 40 to 55 MHz,
assuming all the relavent timing parameters scale (this is what everyone
assumes), the Am29000 would give about 9 to 7 ns for a memory to respond
in one cycle.  Not much, but burst mode is much better leaving about 20
to 15 ns for each sequential access.  This is the price you have to pay
for high performance.

Again, with tail between my legs, let me appologize for so fervently
spouting rubish.

    bcase