Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP
Path: utzoo!mnetor!seismo!husc6!think!ames!oliveb!intelca!mipos3!kds
From: kds@mipos3.UUCP (Ken Shoemaker ~)
Newsgroups: comp.arch
Subject: Re: I-cache prefetch
Message-ID: <681@mipos3.UUCP>
Date: Tue, 19-May-87 15:38:27 EDT
Article-I.D.: mipos3.681
Posted: Tue May 19 15:38:27 1987
Date-Received: Sat, 23-May-87 03:37:58 EDT
References: <765@apple.UUCP> <1551@ames.UUCP>
Reply-To: kds@mipos3.UUCP (Ken Shoemaker ~)
Organization: Intel, Santa Clara, CA
Lines: 14

In article <1551@ames.UUCP> lamaster@ames-pioneer.arpa (Hugh LaMaster) writes:
>Instruction prefetch is one of the many performance benefits derived
>when you separate the instruction cache and the data cache.

of course, seperating the instruction and data caches is not a necessary
condition to allowing instruction prefetch!
-- 
The above views are personal.

...and they whisper and they chatter, but it really doesn't matter.

Ken Shoemaker, Microprocessor Design, Intel Corp., Santa Clara, California
uucp: ...{hplabs|decwrl|amdcad|qantel|pur-ee|scgvaxd|oliveb}!intelca!mipos3!kds
csnet/arpanet: kds@mipos3.intel.com