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From: marc@CS.UCLA.EDU
Newsgroups: comp.lsi
Subject: Register file design
Message-ID: <8705181732.AA14166@zeus.CS.UCLA.EDU>
Date: Mon, 18-May-87 13:32:24 EDT
Article-I.D.: zeus.8705181732.AA14166
Posted: Mon May 18 13:32:24 1987
Date-Received: Tue, 19-May-87 04:14:11 EDT
Sender: daemon@ucbvax.BERKELEY.EDU
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	I am currently designing the datapath of a processor. We
	are implementing some fault-tolerance techniques in the
	design, more specifically around the register file.

	I would like to know if there is any register file design
	available in the following format:
		"MOSIS Scalable CMOS technology"
	
	I am looking for layouts of the following cells:
		- basic register cell (preferably STATIC)
		- register address decoder
		- precharge circuitry
		- sense amplifier

	Thank you for your help,
					Marc Tremblay
					marc@CS.UCLA.EDU