Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Path: utzoo!mnetor!seismo!mcvax!ukc!stl!scott From: scott@stl.stc.co.uk (Mike Scott) Newsgroups: comp.periphs,comp.sys.dec Subject: Q-BUS DMA interprocessor links - DRV11-WA, DRQ11-C, DEQNA Message-ID: <540@acer.stl.stc.co.uk> Date: Tue, 12-May-87 12:08:06 EDT Article-I.D.: acer.540 Posted: Tue May 12 12:08:06 1987 Date-Received: Sat, 16-May-87 04:16:21 EDT Reply-To: scott@stl.UUCP (Mike Scott) Distribution: world Organization: STL,Harlow,UK. Lines: 43 Xref: mnetor comp.periphs:376 comp.sys.dec:193 I have been trying to set up a dma link between 2 Qbus machines (uVAX-VMS and LSI-11/23). This will have to have a sustained data of around 60kbit/sec for several hours. The available DEC boards seem to have problems. Does anyone have any experience with these boards, can anyone tell me what I'm doing wrong (?), or suggest alternative boards? 1. DRV11WA. The hardware book says ok to use as interprocessor link. BUT must start receiver off first. And there's no way to do this without having a working interprocessor link... DEC's solution is for the transmitter to poll its csr to see if the receiver is ready, then to initiate the DMA transfer: but then, why bother with a dma board in the first place?- such a procedure has to be either slow or inefficient. The VMS drivers book says no support for link applications, which isn't very helpful: XADRIVER certainly (even in VMS 4.6) doesn't support the polling DEC are now suggesting, not that I'd care to use that idea. 2. DRQ11CA. Not quite as bad, except that the last transfer can go wrong on output. The board initiates an interrupt before the handshake sequence on the last transfer is complete, so there's a race between the external device reading the last word, and the host starting a new transfer and overwriting it. Not such a problem as for the DRV11WA provided both ends are dma, since bus latency delays are generally short enough that you can afford to wait a little to be sure the last transfer is done. 3. DEQNA The hardware is DMA, but VMS operation involves moving the data between system and user buffers (I think?) and is not efficient enough for my application. My experience anyway is that the DEQNA is not reliable enough- a test program using qio level calls to the DEQNA driver fell over regularly and frequently with an unexplained timeout error status. ---- DEC have not been helpful with these problems. #1 has their comments in it. #2 went round and round their system (in the context of the UNIBUS board, the DRU11CA) before they said "there is no problem" (I gave up eventually!). #3 has been in the DEC system since early March without useful response. ---- Regards, Mike Scott scott@stl.stc.co.uk ...seismo!mcvax!ukc!stl!scott -- Regards Mike Scott ( scott@stl.stc.co.uk +44-279-29531 x3133)