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From: johnw@astroatc.UUCP (John F. Wardale)
Newsgroups: comp.sys.m68k,comp.sys.intel
Subject: Re: Recent Motorola ad seen in Byte
Message-ID: <260@astroatc.UUCP>
Date: Thu, 7-May-87 18:37:20 EDT
Article-I.D.: astroatc.260
Posted: Thu May  7 18:37:20 1987
Date-Received: Sat, 9-May-87 09:35:58 EDT
References: <8705030305.AA18195@cory.Berkeley.EDU> <639@mipos3.UUCP>
Reply-To: johnw@astroatc.UUCP (John F. Wardale)
Organization: Astronautics Technology Cntr, Madison, WI
Lines: 35
Xref: mnetor comp.sys.m68k:458 comp.sys.intel:227

In article <639@mipos3.UUCP> kds@mipos3.UUCP (Ken Shoemaker ~) writes:
	... about specialized string instructions ...
>  For example, in the 386 (and 286) there is special hardware
>in the bus interface unit that is used in the string move instruction to
>effect string transfers at the bus bandwidth.  Trying to do this in a general
>instruction loop would be difficult in that it would require looking at a
>couple of instructions and decoding them as a group.

No, Ken, your looking at this the wrong way.   You are ABSOLUTELY
right that this will be memory (bus) limited.  However, if you can
issue instructions fast enough (by having a fewer, simple
instructions) then a loop can also saturate the memory bus.

(This assumes an I-cache.  If you have to fetch each instruction
on a single memory bus, this will obviously lose!)

Average string length, data caches, MMU's etc. will complicate the
analysis.  Note that a page-fault in the middle of a single instr.
means restarting it, but in the loop case, you just re-issue the
instruction.  This simplification may also help you decrease you
processor's cycle time!

(In case you haven't guessed ... I like RISC)


			John W

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Name:	John F. Wardale
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