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From: wolfgang@haddock.UUCP (Wolfgang Rupprecht)
Newsgroups: comp.arch,comp.sys.m68k
Subject: Re: 68020 speeds and wait states
Message-ID: <494@haddock.UUCP>
Date: Wed, 20-May-87 20:27:15 EDT
Article-I.D.: haddock.494
Posted: Wed May 20 20:27:15 1987
Date-Received: Sat, 23-May-87 10:21:53 EDT
References: <5635@shemp.UCLA.EDU> <1774@im4u.UUCP> <814@killer.UUCP> <2106@hoptoad.uucp> <2728@felix.UUCP> <16650@amdcad.AMD.COM>
Reply-To: wolfgang@haddock.ISC.COM.UUCP (Wolfgang Rupprecht)
Organization: Home for Wayward Programmers
Lines: 18
Xref: mnetor comp.arch:1373 comp.sys.m68k:494

>> ... the fact that the ripple sequence uses
>>rowA8 and colA8 seems to prevent sequencial access, doesn't it?  Doesn't
>>it seem more logical to use colA1 and colA0?
>You can use the pins as you see fit. The pin police will not arrest
>you for reassigning the values. 
>Just move the wires around to give: A0 -> colA8, A1 -> rowA8, and
>connect the rest of the pins in any convenient way. 

The pin police will have a good laugh though, if they see you
refreshing your drams by strobing 2**n SEQUENTIAL addresses
when some of them *don't* go to row-addresses! 

The cheapest way (hardware-wise) to refresh drams is to have a strip
of nops (ie 256 bytes of 'em) that the cpu executes once per refresh
time. This is usually just as fast as some hardware counter doing the
same thing. (Just make sure that your I-cache is turned off!).
-- 
Wolfgang Rupprecht 			haddock.ISC.COM!wolfgang