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From: curtis@cit-vax.Caltech.Edu (shan Curtis)
Newsgroups: rec.aviation,sci.electronics,rec.audio
Subject: DRAMS
Message-ID: <2804@cit-vax.Caltech.Edu>
Date: Sat, 23-May-87 20:41:47 EDT
Article-I.D.: cit-vax.2804
Posted: Sat May 23 20:41:47 1987
Date-Received: Sun, 24-May-87 03:13:44 EDT
Reply-To: curtis@cit-vax.UUCP (Curtis Ling)
Organization: California Institute of Technology
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Xref: mnetor rec.aviation:1670 sci.electronics:734 rec.audio:1714

References:



If I'm using DRAMS (Fujitsu MB81257-12) only in Read, Write and CAS-before
RAS refresh, it would appear from looking at the  timing diagrams, that 
the Q line (data out)is always hi-Z until read cycles.  Is it ok to connect
the Q and D lines together and directly to the bus, thereby avoiding having
to use buffers?  Thanks for the help in advance.  

Curtis
ccl@juliet.caltech.edu
curtis@cit-vax.caltech.edu