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From: grr@cbmvax.cbm.UUCP (George Robbins)
Newsgroups: rec.aviation,sci.electronics,rec.audio
Subject: Re: DRAMS
Message-ID: <1921@cbmvax.cbmvax.cbm.UUCP>
Date: Sun, 24-May-87 07:13:11 EDT
Article-I.D.: cbmvax.1921
Posted: Sun May 24 07:13:11 1987
Date-Received: Sun, 24-May-87 19:44:41 EDT
References: <2804@cit-vax.Caltech.Edu>
Reply-To: grr@cbmvax.UUCP (George Robbins)
Organization: Commodore Technology, West Chester, PA
Lines: 23
Xref: mnetor rec.aviation:1673 sci.electronics:736 rec.audio:1718

In article <2804@cit-vax.Caltech.Edu> curtis@cit-vax.UUCP (Curtis Ling) writes:
> 
> If I'm using DRAMS (Fujitsu MB81257-12) only in Read, Write and CAS-before
> RAS refresh, it would appear from looking at the  timing diagrams, that 
> the Q line (data out)is always hi-Z until read cycles.  Is it ok to connect
> the Q and D lines together and directly to the bus, thereby avoiding having
> to use buffers?  Thanks for the help in advance.  
> 
> Curtis  ccl@juliet.caltech.edu

As a general rule, you can tie data in and data out together as long as your
write signal is asserted before CAS.  Whether you can tie the rams directly
to a bus is more complicated, but as long as you understand that CAS is, in
effect, an output enable signal, you can avoid conflicts.  If you are planning
on connecting to some kind of "external" microcomputer bus, you will probably
need some kind of buffers for reliable operation.  Also, do not neglect series
termination resistors on address and control lines, and proper layout and
decoupling.  DRAM's *can* be a real pain in the ass unless treated with the
proper degree of respect.
-- 
George Robbins - now working for,	uucp: {ihnp4|seismo|rutgers}!cbmvax!grr
but no way officially representing	arpa: cbmvax!grr@seismo.css.GOV
Commodore, Engineering Department	fone: 215-431-9255 (only by moonlite)