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From: phil@amdcad.AMD.COM (Phil Ngai)
Newsgroups: rec.aviation,sci.electronics,rec.audio
Subject: Re: DRAMS
Message-ID: <16818@amdcad.AMD.COM>
Date: Tue, 26-May-87 14:37:52 EDT
Article-I.D.: amdcad.16818
Posted: Tue May 26 14:37:52 1987
Date-Received: Thu, 28-May-87 03:14:01 EDT
References: <2804@cit-vax.Caltech.Edu>
Reply-To: phil@amdcad.UUCP (Phil Ngai)
Organization: Advanced Micro Devices, Inc., Sunnyvale, Ca.
Lines: 34
Xref: mnetor rec.aviation:1690 sci.electronics:751 rec.audio:1738

In article <2804@cit-vax.Caltech.Edu> curtis@cit-vax.UUCP (Curtis Ling) writes:
>
>If I'm using DRAMS (Fujitsu MB81257-12) only in Read, Write and CAS-before
>RAS refresh, it would appear from looking at the  timing diagrams, that 
>the Q line (data out)is always hi-Z until read cycles.  Is it ok to connect
>the Q and D lines together and directly to the bus, thereby avoiding having
>to use buffers?  Thanks for the help in advance.  

This kind of thing can work, as I have done it in a product. Note,
that one of the claimed features is "Common I/O capability using
'Early Write' operation". 

Some important considerations are

1) are you doing early write cycles? If you are doing late writes, the
RAM will probably experience a bus collision with the device doing the
write until you assert *W. This is because the RAM doesn't know you're
not doing a read cycle until *W is activated.

2) Also check the load capacitance presented to each of the drivers on
the data bus.  DRAMs generally drive 100 pF and present about 7 pF on
each of D and Q. 

3) All the usual stuff about good bypassing, transmission line
effects, motherhood and apple pie. If you only have 16 devices or so
you can afford to be somewhat sloppy (that's the number I used and the
signals were super clean) and with 64 you have to be more careful.
There are special RAM drivers with series termination resistors in the
IC, these provide faster drive with more symmetric rise and fall
times. Look for the 2965 or 2966. 

What is this doing in rec.aviation?
-- 
Phil Ngai, {ucbvax,decwrl,allegra}!amdcad!phil or amdcad!phil@decwrl.dec.com