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From: jack@mcvax.UUCP
Newsgroups: comp.arch
Subject: Interrupt vectors.
Message-ID: <7408@boring.cwi.nl>
Date: Thu, 4-Jun-87 15:56:03 EDT
Article-I.D.: boring.7408
Posted: Thu Jun  4 15:56:03 1987
Date-Received: Sat, 6-Jun-87 11:16:45 EDT
Organization: AMOEBA project, CWI, Amsterdam
Lines: 28


I was just wondering wether any of the fancy new machines (MIPS,
AMD) did anything about the stupid way interrupts are done in
most modern machines.

Almost all machines I know of provide a list of interrupt vectors
which consist of a program counter, and (sometimes) a module base
address or a PSR.

Now, given most modern operating systems, this is exactly what you
*don't* want. If you want to handle interrupts in a high-level
language, you want all interrupts to jump to the same routine, and
have the interrupt number handy somewhere. Operating Systems I'm
familiar with all simulate this by either stealing a couple of bits
in the PSR and go through pains to extract them again in the common
interrupt routine, or, even worse, provide lots and lots of twisty little
routines, all slightly different (like
intvec128:	push	#128.
		jmp	int_common	).

Now, the sensible thing for the hardware to do seems to be to
provide one vector, and push the interrupt number along with the
PC, PSW and what have you.

Is this scheme implemented on any machine?
-- 
	Jack Jansen, jack@cwi.nl (or jack@mcvax.uucp)
	The shell is my oyster.