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From: rpw3@amdcad.UUCP
Newsgroups: comp.arch
Subject: Re: Interrupt vectors.
Message-ID: <17023@amdcad.AMD.COM>
Date: Fri, 5-Jun-87 17:01:42 EDT
Article-I.D.: amdcad.17023
Posted: Fri Jun  5 17:01:42 1987
Date-Received: Sat, 6-Jun-87 20:07:36 EDT
References: <7408@boring.cwi.nl> <438@winchester.UUCP>
Reply-To: rpw3@amdcad.UUCP (Rob Warnock)
Organization: [Consultant] San Mateo, CA
Lines: 20

In article <7408@boring.cwi.nl> jack@cwi.nl (Jack Jansen) writes:
>Now, the sensible thing for the hardware to do seems to be to
>provide one vector, and push the interrupt number along with the
>PC, PSW and what have you.
>Is this scheme implemented on any machine?

Yup! (Almost.) The IBM/370 architecture (in "EC mode") provides one
vector for each major class of event, where all I/O is one class, and
a nice "reason" code which then tells you the specific channel/device
(or interrupt cause for non-I/O), etc. (No flames about all the *other*
uglinesses of 370 interrupts, please! It does what he asked...)


Rob Warnock
Systems Architecture Consultant

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