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From: csg@pyramid.UUCP
Newsgroups: comp.arch
Subject: Re: Interrupt vectors.
Message-ID: <2909@pyramid.UUCP>
Date: Sat, 6-Jun-87 14:36:49 EDT
Article-I.D.: pyramid.2909
Posted: Sat Jun  6 14:36:49 1987
Date-Received: Sun, 7-Jun-87 20:49:37 EDT
References: <7408@boring.cwi.nl> <2878@pyramid.UUCP> <19253@ucbvax.BERKELEY.EDU>
Reply-To: csg@pyramid.UUCP (Carl S. Gutekunst)
Distribution: world
Organization: Pyramid Technology Corp., Mountain View, CA
Lines: 15
Keywords: interrupt handlers

<<<If you want to handle interrupts in a high-level language, you want all
<<<interrupts to jump to the same routine, and have the interrupt number handy
<<<somewhere.
<<
<<I can't for the life of me see why you'd want this.
<
<Assume a machine (when it interrupts) (like a 68010, 68020) pushes
<the PSW, PC, and the interrupt vector number....

Pardon my blinders, I wasn't thinking. The Pyramid 90x, which has a register
architecture, is hardly representive of the entire world. (All I had to do was
go back and look at my own O/S code for PDP-11, 68000, Z80, and Z8. Gee, it
would have been handy it they'd used a single interrupt entry point... *SIGH*) 

<csg>