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From: mac@uvacs.CS.VIRGINIA.EDU (Alex Colvin)
Newsgroups: comp.arch
Subject: Re: Interrupt vectors.
Message-ID: <1548@uvacs.CS.VIRGINIA.EDU>
Date: Fri, 5-Jun-87 13:32:19 EDT
Article-I.D.: uvacs.1548
Posted: Fri Jun  5 13:32:19 1987
Date-Received: Wed, 10-Jun-87 02:32:26 EDT
References: <7408@boring.cwi.nl>
Organization: University of Virginia
Lines: 19
Summary: interrupt entries

In article <7408@boring.cwi.nl>, jack@cwi.nl (Jack Jansen) writes:
> you want all interrupts to jump to the same routine, and
> have the interrupt number handy somewhere. Operating Systems I'm
> familiar with all simulate this ...

> Now, the sensible thing for the hardware to do seems to be to
> provide one vector, and push the interrupt number along with the
> PC, PSW and what have you.
> 
> Is this scheme implemented on any machine?

Almost.  The system you complain about tends to prevail on
microcomputers more than mainframes.  Those (Honeywell) mainframes with
which I was familiar have a single interrupt entry for I/O interrupts.
You are then provided a bit mask of channels attempting an interrupt.
Handles the case of simultaneous interrupts nicely.

Instruction faults are handled differently, each with its own entry,
which makes some sense.  You probably don't want to schedule these.