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From: daveb@geac.UUCP (Dave Brown)
Newsgroups: comp.arch
Subject: Pipelines (Formerly Benchmarking the 432)
Message-ID: <785@geac.UUCP>
Date: Tue, 16-Jun-87 09:58:31 EDT
Article-I.D.: geac.785
Posted: Tue Jun 16 09:58:31 1987
Date-Received: Wed, 17-Jun-87 00:37:27 EDT
References: <324@dumbo.UUCP> <809@killer.UUCP> <2417@homxa.UUCP>
Reply-To: daveb@geac.UUCP (Dave Brown)
Organization: GEAC Computers, Toronto, CANADA
Lines: 32
Summary: Having more than one pipeline helps.

In article <847@polaris.UUCP> josh@polaris.UUCP (Josh Knight) writes:
>
>In article <202@celerity.UUCP> ps@celerity.UUCP (Pat Shanahan) writes:
>Even when the machines have the same architecture, performance is not
>a one number affair.  Consider the case of two implementations of the
>IBM 370 architecture, the 3033 and the 3090.  Both are pipelined, indeed
>the 3090 is a *VERY* close relative of the 3033.  In his description
>of the 3090 (IBM Systems Journal, Vol. 25, No. 1, 1986, pp. 4-19), Stu
>Tucker comments:
>     ...
>    the only branches left that need to be guessed are branch-on-
>    condition-code instructions that actually do have a condition-
>    code setting operation ahead of them in the pipeline.  For them,
>    a decode history-table scheme is used, in which a table keeps
>    the history of branches.
>     ...

    Apropos of this side comment on pipelines and conditional branches,
I notice that Nippon Electric Company (NEC) have introduced a triple-
pipeline mechanism in their Honeywell-architecture "90"s.
    It seems that for a given number of stages required to decode
instructions and a total pipeline length, one can define the number of
secondary pipelines required to prepare and decode instructions which
lie on the two possible branches of a conditional jump instruction.
Whats more, the number tends to be very small: 3 is sufficient on even
a Vcisc machine like the big 'bun, for over 90% of all possible
sequences of test/branch/test/branch... instructions.
    This un-bottlenecks one of the hot spots in that particular machine,
which suffers from a long instruction prep/decode process because of 
its considerable complexity.

 --dave